Texas Instruments MSP432P401VTRGC 2024.11.10 MSP432P401VTRGC false ADC14 ADC14 ADC14 0x40012000 0x0 0x158 registers n ADC14_IRQ ADC14 Interrupt 24 ADC14CLRIFGR0 CLRIFGR0 Clear Interrupt Flag 0 Register 0x14C 32 write-only n 0x0 0xFFFFFFFF CLRADC14IFG0 clear ADC14IFG0 0 1 write-only CLRADC14IFG0_enum_write write CLRADC14IFG0_0 no effect 0 CLRADC14IFG0_1 clear pending interrupt flag 1 CLRADC14IFG1 clear ADC14IFG1 1 1 write-only CLRADC14IFG1_enum_write write CLRADC14IFG1_0 no effect 0 CLRADC14IFG1_1 clear pending interrupt flag 1 CLRADC14IFG10 clear ADC14IFG10 10 1 write-only CLRADC14IFG10_enum_write write CLRADC14IFG10_0 no effect 0 CLRADC14IFG10_1 clear pending interrupt flag 1 CLRADC14IFG11 clear ADC14IFG11 11 1 write-only CLRADC14IFG11_enum_write write CLRADC14IFG11_0 no effect 0 CLRADC14IFG11_1 clear pending interrupt flag 1 CLRADC14IFG12 clear ADC14IFG12 12 1 write-only CLRADC14IFG12_enum_write write CLRADC14IFG12_0 no effect 0 CLRADC14IFG12_1 clear pending interrupt flag 1 CLRADC14IFG13 clear ADC14IFG13 13 1 write-only CLRADC14IFG13_enum_write write CLRADC14IFG13_0 no effect 0 CLRADC14IFG13_1 clear pending interrupt flag 1 CLRADC14IFG14 clear ADC14IFG14 14 1 write-only CLRADC14IFG14_enum_write write CLRADC14IFG14_0 no effect 0 CLRADC14IFG14_1 clear pending interrupt flag 1 CLRADC14IFG15 clear ADC14IFG15 15 1 write-only CLRADC14IFG15_enum_write write CLRADC14IFG15_0 no effect 0 CLRADC14IFG15_1 clear pending interrupt flag 1 CLRADC14IFG16 clear ADC14IFG16 16 1 write-only CLRADC14IFG16_enum_write write CLRADC14IFG16_0 no effect 0 CLRADC14IFG16_1 clear pending interrupt flag 1 CLRADC14IFG17 clear ADC14IFG17 17 1 write-only CLRADC14IFG17_enum_write write CLRADC14IFG17_0 no effect 0 CLRADC14IFG17_1 clear pending interrupt flag 1 CLRADC14IFG18 clear ADC14IFG18 18 1 write-only CLRADC14IFG18_enum_write write CLRADC14IFG18_0 no effect 0 CLRADC14IFG18_1 clear pending interrupt flag 1 CLRADC14IFG19 clear ADC14IFG19 19 1 write-only CLRADC14IFG19_enum_write write CLRADC14IFG19_0 no effect 0 CLRADC14IFG19_1 clear pending interrupt flag 1 CLRADC14IFG2 clear ADC14IFG2 2 1 write-only CLRADC14IFG2_enum_write write CLRADC14IFG2_0 no effect 0 CLRADC14IFG2_1 clear pending interrupt flag 1 CLRADC14IFG20 clear ADC14IFG20 20 1 write-only CLRADC14IFG20_enum_write write CLRADC14IFG20_0 no effect 0 CLRADC14IFG20_1 clear pending interrupt flag 1 CLRADC14IFG21 clear ADC14IFG21 21 1 write-only CLRADC14IFG21_enum_write write CLRADC14IFG21_0 no effect 0 CLRADC14IFG21_1 clear pending interrupt flag 1 CLRADC14IFG22 clear ADC14IFG22 22 1 write-only CLRADC14IFG22_enum_write write CLRADC14IFG22_0 no effect 0 CLRADC14IFG22_1 clear pending interrupt flag 1 CLRADC14IFG23 clear ADC14IFG23 23 1 write-only CLRADC14IFG23_enum_write write CLRADC14IFG23_0 no effect 0 CLRADC14IFG23_1 clear pending interrupt flag 1 CLRADC14IFG24 clear ADC14IFG24 24 1 write-only CLRADC14IFG24_enum_write write CLRADC14IFG24_0 no effect 0 CLRADC14IFG24_1 clear pending interrupt flag 1 CLRADC14IFG25 clear ADC14IFG25 25 1 write-only CLRADC14IFG25_enum_write write CLRADC14IFG25_0 no effect 0 CLRADC14IFG25_1 clear pending interrupt flag 1 CLRADC14IFG26 clear ADC14IFG26 26 1 write-only CLRADC14IFG26_enum_write write CLRADC14IFG26_0 no effect 0 CLRADC14IFG26_1 clear pending interrupt flag 1 CLRADC14IFG27 clear ADC14IFG27 27 1 write-only CLRADC14IFG27_enum_write write CLRADC14IFG27_0 no effect 0 CLRADC14IFG27_1 clear pending interrupt flag 1 CLRADC14IFG28 clear ADC14IFG28 28 1 write-only CLRADC14IFG28_enum_write write CLRADC14IFG28_0 no effect 0 CLRADC14IFG28_1 clear pending interrupt flag 1 CLRADC14IFG29 clear ADC14IFG29 29 1 write-only CLRADC14IFG29_enum_write write CLRADC14IFG29_0 no effect 0 CLRADC14IFG29_1 clear pending interrupt flag 1 CLRADC14IFG3 clear ADC14IFG3 3 1 write-only CLRADC14IFG3_enum_write write CLRADC14IFG3_0 no effect 0 CLRADC14IFG3_1 clear pending interrupt flag 1 CLRADC14IFG30 clear ADC14IFG30 30 1 write-only CLRADC14IFG30_enum_write write CLRADC14IFG30_0 no effect 0 CLRADC14IFG30_1 clear pending interrupt flag 1 CLRADC14IFG31 clear ADC14IFG31 31 1 write-only CLRADC14IFG31_enum_write write CLRADC14IFG31_0 no effect 0 CLRADC14IFG31_1 clear pending interrupt flag 1 CLRADC14IFG4 clear ADC14IFG4 4 1 write-only CLRADC14IFG4_enum_write write CLRADC14IFG4_0 no effect 0 CLRADC14IFG4_1 clear pending interrupt flag 1 CLRADC14IFG5 clear ADC14IFG5 5 1 write-only CLRADC14IFG5_enum_write write CLRADC14IFG5_0 no effect 0 CLRADC14IFG5_1 clear pending interrupt flag 1 CLRADC14IFG6 clear ADC14IFG6 6 1 write-only CLRADC14IFG6_enum_write write CLRADC14IFG6_0 no effect 0 CLRADC14IFG6_1 clear pending interrupt flag 1 CLRADC14IFG7 clear ADC14IFG7 7 1 write-only CLRADC14IFG7_enum_write write CLRADC14IFG7_0 no effect 0 CLRADC14IFG7_1 clear pending interrupt flag 1 CLRADC14IFG8 clear ADC14IFG8 8 1 write-only CLRADC14IFG8_enum_write write CLRADC14IFG8_0 no effect 0 CLRADC14IFG8_1 clear pending interrupt flag 1 CLRADC14IFG9 clear ADC14IFG9 9 1 write-only CLRADC14IFG9_enum_write write CLRADC14IFG9_0 no effect 0 CLRADC14IFG9_1 clear pending interrupt flag 1 ADC14CLRIFGR1 CLRIFGR1 Clear Interrupt Flag 1 Register 0x150 32 read-write n 0x0 0xFFFFFFFF CLRADC14HIIFG clear ADC14HIIFG 3 1 write-only CLRADC14HIIFG_enum_write write CLRADC14HIIFG_0 no effect 0 CLRADC14HIIFG_1 clear pending interrupt flag 1 CLRADC14INIFG clear ADC14INIFG 1 1 write-only CLRADC14INIFG_enum_write write CLRADC14INIFG_0 no effect 0 CLRADC14INIFG_1 clear pending interrupt flag 1 CLRADC14LOIFG clear ADC14LOIFG 2 1 write-only CLRADC14LOIFG_enum_write write CLRADC14LOIFG_0 no effect 0 CLRADC14LOIFG_1 clear pending interrupt flag 1 CLRADC14OVIFG clear ADC14OVIFG 4 1 write-only CLRADC14OVIFG_enum_write write CLRADC14OVIFG_0 no effect 0 CLRADC14OVIFG_1 clear pending interrupt flag 1 CLRADC14RDYIFG clear ADC14RDYIFG 6 1 write-only CLRADC14RDYIFG_enum_write write CLRADC14RDYIFG_0 no effect 0 CLRADC14RDYIFG_1 clear pending interrupt flag 1 CLRADC14TOVIFG clear ADC14TOVIFG 5 1 write-only CLRADC14TOVIFG_enum_write write CLRADC14TOVIFG_0 no effect 0 CLRADC14TOVIFG_1 clear pending interrupt flag 1 ADC14CTL0 CTL0 Control 0 Register 0x0 32 read-write n 0x0 0xFFFFFFFF ADC14BUSY ADC14 busy 16 1 read-only ADC14BUSY_enum_read read ADC14BUSY_0 No operation is active 0 ADC14BUSY_1 A sequence, sample, or conversion is active 1 ADC14CONSEQ ADC14 conversion sequence mode select 17 2 read-write ADC14CONSEQ_0 Single-channel, single-conversion 0 ADC14CONSEQ_1 Sequence-of-channels 1 ADC14CONSEQ_2 Repeat-single-channel 2 ADC14CONSEQ_3 Repeat-sequence-of-channels 3 ADC14DIV ADC14 clock divider 22 3 read-write ADC14DIV_0 /1 0 ADC14DIV_1 /2 1 ADC14DIV_2 /3 2 ADC14DIV_3 /4 3 ADC14DIV_4 /5 4 ADC14DIV_5 /6 5 ADC14DIV_6 /7 6 ADC14DIV_7 /8 7 ADC14ENC ADC14 enable conversion 1 1 read-write ADC14ENC_0 ADC14 disabled 0 ADC14ENC_1 ADC14 enabled 1 ADC14ISSH ADC14 invert signal sample-and-hold 25 1 read-write ADC14ISSH_0 The sample-input signal is not inverted 0 ADC14ISSH_1 The sample-input signal is inverted 1 ADC14MSC ADC14 multiple sample and conversion 7 1 read-write ADC14MSC_0 The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-convert 0 ADC14MSC_1 The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-conversions are performed automatically as soon as the prior conversion is completed 1 ADC14ON ADC14 on 4 1 read-write ADC14ON_0 ADC14 off 0 ADC14ON_1 ADC14 on. ADC core is ready to power up when a valid conversion is triggered. 1 ADC14PDIV ADC14 predivider 30 2 read-write ADC14PDIV_0 Predivide by 1 0 ADC14PDIV_1 Predivide by 4 1 ADC14PDIV_2 Predivide by 32 2 ADC14PDIV_3 Predivide by 64 3 ADC14SC ADC14 start conversion 0 1 read-write ADC14SC_0 No sample-and-conversion-start 0 ADC14SC_1 Start sample-and-conversion 1 ADC14SHP ADC14 sample-and-hold pulse-mode select 26 1 read-write ADC14SHP_0 SAMPCON signal is sourced from the sample-input signal 0 ADC14SHP_1 SAMPCON signal is sourced from the sampling timer 1 ADC14SHS ADC14 sample-and-hold source select 27 3 read-write ADC14SHS_0 ADC14SC bit 0 ADC14SHS_1 See device-specific data sheet for source 1 ADC14SHS_2 See device-specific data sheet for source 2 ADC14SHS_3 See device-specific data sheet for source 3 ADC14SHS_4 See device-specific data sheet for source 4 ADC14SHS_5 See device-specific data sheet for source 5 ADC14SHS_6 See device-specific data sheet for source 6 ADC14SHS_7 See device-specific data sheet for source 7 ADC14SHT0 ADC14 sample-and-hold time 8 4 read-write ADC14SHT0_0 4 0 ADC14SHT0_1 8 1 ADC14SHT0_2 16 2 ADC14SHT0_3 32 3 ADC14SHT0_4 64 4 ADC14SHT0_5 96 5 ADC14SHT0_6 128 6 ADC14SHT0_7 192 7 ADC14SHT1 ADC14 sample-and-hold time 12 4 read-write ADC14SHT1_0 4 0 ADC14SHT1_1 8 1 ADC14SHT1_2 16 2 ADC14SHT1_3 32 3 ADC14SHT1_4 64 4 ADC14SHT1_5 96 5 ADC14SHT1_6 128 6 ADC14SHT1_7 192 7 ADC14SSEL ADC14 clock source select 19 3 read-write ADC14SSEL_0 MODCLK 0 ADC14SSEL_1 SYSCLK 1 ADC14SSEL_2 ACLK 2 ADC14SSEL_3 MCLK 3 ADC14SSEL_4 SMCLK 4 ADC14SSEL_5 HSMCLK 5 ADC14CTL1 CTL1 Control 1 Register 0x4 32 read-write n 0x30 0xFFFFFFFF ADC14BATMAP Controls 1/2 AVCC ADC input channel selection 22 1 read-write ADC14BATMAP_0 ADC internal 1/2 x AVCC channel is not selected for ADC 0 ADC14BATMAP_1 ADC internal 1/2 x AVCC channel is selected for ADC input channel MAX 1 ADC14CH0MAP Controls internal channel 0 selection to ADC input channel MAX-2 24 1 read-write ADC14CH0MAP_0 ADC input channel internal 0 is not selected 0 ADC14CH0MAP_1 ADC input channel internal 0 is selected for ADC input channel MAX-2 1 ADC14CH1MAP Controls internal channel 1 selection to ADC input channel MAX-3 25 1 read-write ADC14CH1MAP_0 ADC input channel internal 1 is not selected 0 ADC14CH1MAP_1 ADC input channel internal 1 is selected for ADC input channel MAX-3 1 ADC14CH2MAP Controls internal channel 2 selection to ADC input channel MAX-4 26 1 read-write ADC14CH2MAP_0 ADC input channel internal 2 is not selected 0 ADC14CH2MAP_1 ADC input channel internal 2 is selected for ADC input channel MAX-4 1 ADC14CH3MAP Controls internal channel 3 selection to ADC input channel MAX-5 27 1 read-write ADC14CH3MAP_0 ADC input channel internal 3 is not selected 0 ADC14CH3MAP_1 ADC input channel internal 3 is selected for ADC input channel MAX-5 1 ADC14CSTARTADD ADC14 conversion start address 16 5 read-write ADC14DF ADC14 data read-back format 3 1 read-write ADC14DF_0 Binary unsigned. Theoretically, for ADC14DIF = 0 and 14-bit mode, the analog input voltage - V(REF) results in 0000h, and the analog input voltage + V(REF) results in 3FFFh 0 ADC14DF_1 Signed binary (2s complement), left aligned. Theoretically, for ADC14DIF = 0 and 14-bit mode, the analog input voltage - V(REF) results in 8000h, and the analog input voltage + V(REF) results in 7FFCh 1 ADC14PWRMD ADC14 power modes 0 2 read-write ADC14PWRMD_0 Regular power mode for use with any resolution setting. Sample rate can be up to 1 Msps. 0 ADC14PWRMD_2 Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample rate must not exceed 200 ksps. 2 ADC14REFBURST ADC14 reference buffer burst 2 1 read-write ADC14REFBURST_0 ADC reference buffer on continuously 0 ADC14REFBURST_1 ADC reference buffer on only during sample-and-conversion 1 ADC14RES ADC14 resolution 4 2 read-write ADC14RES_0 8 bit (9 clock cycle conversion time) 0 ADC14RES_1 10 bit (11 clock cycle conversion time) 1 ADC14RES_2 12 bit (14 clock cycle conversion time) 2 ADC14RES_3 14 bit (16 clock cycle conversion time) 3 ADC14TCMAP Controls temperature sensor ADC input channel selection 23 1 read-write ADC14TCMAP_0 ADC internal temperature sensor channel is not selected for ADC 0 ADC14TCMAP_1 ADC internal temperature sensor channel is selected for ADC input channel MAX-1 1 ADC14HI0 HI0 Window Comparator High Threshold 0 Register 0xC 32 read-write n 0x3FFF 0xFFFFFFFF ADC14HI0 High threshold 0 0 16 read-write ADC14HI1 HI1 Window Comparator High Threshold 1 Register 0x14 32 read-write n 0x3FFF 0xFFFFFFFF ADC14HI1 High threshold 1 0 16 read-write ADC14IER0 IER0 Interrupt Enable 0 Register 0x13C 32 read-write n 0x0 0xFFFFFFFF ADC14IE0 Interrupt enable 0 1 read-write ADC14IE0_0 Interrupt disabled 0 ADC14IE0_1 Interrupt enabled 1 ADC14IE1 Interrupt enable 1 1 read-write ADC14IE1_0 Interrupt disabled 0 ADC14IE1_1 Interrupt enabled 1 ADC14IE10 Interrupt enable 10 1 read-write ADC14IE10_0 Interrupt disabled 0 ADC14IE10_1 Interrupt enabled 1 ADC14IE11 Interrupt enable 11 1 read-write ADC14IE11_0 Interrupt disabled 0 ADC14IE11_1 Interrupt enabled 1 ADC14IE12 Interrupt enable 12 1 read-write ADC14IE12_0 Interrupt disabled 0 ADC14IE12_1 Interrupt enabled 1 ADC14IE13 Interrupt enable 13 1 read-write ADC14IE13_0 Interrupt disabled 0 ADC14IE13_1 Interrupt enabled 1 ADC14IE14 Interrupt enable 14 1 read-write ADC14IE14_0 Interrupt disabled 0 ADC14IE14_1 Interrupt enabled 1 ADC14IE15 Interrupt enable 15 1 read-write ADC14IE15_0 Interrupt disabled 0 ADC14IE15_1 Interrupt enabled 1 ADC14IE16 Interrupt enable 16 1 read-write ADC14IE16_0 Interrupt disabled 0 ADC14IE16_1 Interrupt enabled 1 ADC14IE17 Interrupt enable 17 1 read-write ADC14IE17_0 Interrupt disabled 0 ADC14IE17_1 Interrupt enabled 1 ADC14IE18 Interrupt enable 18 1 read-write ADC14IE18_0 Interrupt disabled 0 ADC14IE18_1 Interrupt enabled 1 ADC14IE19 Interrupt enable 19 1 read-write ADC14IE19_0 Interrupt disabled 0 ADC14IE19_1 Interrupt enabled 1 ADC14IE2 Interrupt enable 2 1 read-write ADC14IE2_0 Interrupt disabled 0 ADC14IE2_1 Interrupt enabled 1 ADC14IE20 Interrupt enable 20 1 read-write ADC14IE20_0 Interrupt disabled 0 ADC14IE20_1 Interrupt enabled 1 ADC14IE21 Interrupt enable 21 1 read-write ADC14IE21_0 Interrupt disabled 0 ADC14IE21_1 Interrupt enabled 1 ADC14IE22 Interrupt enable 22 1 read-write ADC14IE22_0 Interrupt disabled 0 ADC14IE22_1 Interrupt enabled 1 ADC14IE23 Interrupt enable 23 1 read-write ADC14IE23_0 Interrupt disabled 0 ADC14IE23_1 Interrupt enabled 1 ADC14IE24 Interrupt enable 24 1 read-write ADC14IE24_0 Interrupt disabled 0 ADC14IE24_1 Interrupt enabled 1 ADC14IE25 Interrupt enable 25 1 read-write ADC14IE25_0 Interrupt disabled 0 ADC14IE25_1 Interrupt enabled 1 ADC14IE26 Interrupt enable 26 1 read-write ADC14IE26_0 Interrupt disabled 0 ADC14IE26_1 Interrupt enabled 1 ADC14IE27 Interrupt enable 27 1 read-write ADC14IE27_0 Interrupt disabled 0 ADC14IE27_1 Interrupt enabled 1 ADC14IE28 Interrupt enable 28 1 read-write ADC14IE28_0 Interrupt disabled 0 ADC14IE28_1 Interrupt enabled 1 ADC14IE29 Interrupt enable 29 1 read-write ADC14IE29_0 Interrupt disabled 0 ADC14IE29_1 Interrupt enabled 1 ADC14IE3 Interrupt enable 3 1 read-write ADC14IE3_0 Interrupt disabled 0 ADC14IE3_1 Interrupt enabled 1 ADC14IE30 Interrupt enable 30 1 read-write ADC14IE30_0 Interrupt disabled 0 ADC14IE30_1 Interrupt enabled 1 ADC14IE31 Interrupt enable 31 1 read-write ADC14IE31_0 Interrupt disabled 0 ADC14IE31_1 Interrupt enabled 1 ADC14IE4 Interrupt enable 4 1 read-write ADC14IE4_0 Interrupt disabled 0 ADC14IE4_1 Interrupt enabled 1 ADC14IE5 Interrupt enable 5 1 read-write ADC14IE5_0 Interrupt disabled 0 ADC14IE5_1 Interrupt enabled 1 ADC14IE6 Interrupt enable 6 1 read-write ADC14IE6_0 Interrupt disabled 0 ADC14IE6_1 Interrupt enabled 1 ADC14IE7 Interrupt enable 7 1 read-write ADC14IE7_0 Interrupt disabled 0 ADC14IE7_1 Interrupt enabled 1 ADC14IE8 Interrupt enable 8 1 read-write ADC14IE8_0 Interrupt disabled 0 ADC14IE8_1 Interrupt enabled 1 ADC14IE9 Interrupt enable 9 1 read-write ADC14IE9_0 Interrupt disabled 0 ADC14IE9_1 Interrupt enabled 1 ADC14IER1 IER1 Interrupt Enable 1 Register 0x140 32 read-write n 0x0 0xFFFFFFFF ADC14HIIE Interrupt enable for ADC14MEMx above comparator window 3 1 read-write ADC14HIIE_0 Interrupt disabled 0 ADC14HIIE_1 Interrupt enabled 1 ADC14INIE Interrupt enable for ADC14MEMx within comparator window 1 1 read-write ADC14INIE_0 Interrupt disabled 0 ADC14INIE_1 Interrupt enabled 1 ADC14LOIE Interrupt enable for ADC14MEMx below comparator window 2 1 read-write ADC14LOIE_0 Interrupt disabled 0 ADC14LOIE_1 Interrupt enabled 1 ADC14OVIE ADC14MEMx overflow-interrupt enable 4 1 read-write ADC14OVIE_0 Interrupt disabled 0 ADC14OVIE_1 Interrupt enabled 1 ADC14RDYIE ADC14 local buffered reference ready interrupt enable 6 1 read-write ADC14RDYIE_0 Interrupt disabled 0 ADC14RDYIE_1 Interrupt enabled 1 ADC14TOVIE ADC14 conversion-time-overflow interrupt enable 5 1 read-write ADC14TOVIE_0 Interrupt disabled 0 ADC14TOVIE_1 Interrupt enabled 1 ADC14IFGR0 IFGR0 Interrupt Flag 0 Register 0x144 32 read-only n 0x0 0xFFFFFFFF ADC14IFG0 ADC14MEM0 interrupt flag 0 1 read-only ADC14IFG0_enum_read read ADC14IFG0_0 No interrupt pending 0 ADC14IFG0_1 Interrupt pending 1 ADC14IFG1 ADC14MEM1 interrupt flag 1 1 read-only ADC14IFG1_enum_read read ADC14IFG1_0 No interrupt pending 0 ADC14IFG1_1 Interrupt pending 1 ADC14IFG10 ADC14MEM10 interrupt flag 10 1 read-only ADC14IFG10_enum_read read ADC14IFG10_0 No interrupt pending 0 ADC14IFG10_1 Interrupt pending 1 ADC14IFG11 ADC14MEM11 interrupt flag 11 1 read-only ADC14IFG11_enum_read read ADC14IFG11_0 No interrupt pending 0 ADC14IFG11_1 Interrupt pending 1 ADC14IFG12 ADC14MEM12 interrupt flag 12 1 read-only ADC14IFG12_enum_read read ADC14IFG12_0 No interrupt pending 0 ADC14IFG12_1 Interrupt pending 1 ADC14IFG13 ADC14MEM13 interrupt flag 13 1 read-only ADC14IFG13_enum_read read ADC14IFG13_0 No interrupt pending 0 ADC14IFG13_1 Interrupt pending 1 ADC14IFG14 ADC14MEM14 interrupt flag 14 1 read-only ADC14IFG14_enum_read read ADC14IFG14_0 No interrupt pending 0 ADC14IFG14_1 Interrupt pending 1 ADC14IFG15 ADC14MEM15 interrupt flag 15 1 read-only ADC14IFG15_enum_read read ADC14IFG15_0 No interrupt pending 0 ADC14IFG15_1 Interrupt pending 1 ADC14IFG16 ADC14MEM16 interrupt flag 16 1 read-only ADC14IFG16_enum_read read ADC14IFG16_0 No interrupt pending 0 ADC14IFG16_1 Interrupt pending 1 ADC14IFG17 ADC14MEM17 interrupt flag 17 1 read-only ADC14IFG17_enum_read read ADC14IFG17_0 No interrupt pending 0 ADC14IFG17_1 Interrupt pending 1 ADC14IFG18 ADC14MEM18 interrupt flag 18 1 read-only ADC14IFG18_enum_read read ADC14IFG18_0 No interrupt pending 0 ADC14IFG18_1 Interrupt pending 1 ADC14IFG19 ADC14MEM19 interrupt flag 19 1 read-only ADC14IFG19_enum_read read ADC14IFG19_0 No interrupt pending 0 ADC14IFG19_1 Interrupt pending 1 ADC14IFG2 ADC14MEM2 interrupt flag 2 1 read-only ADC14IFG2_enum_read read ADC14IFG2_0 No interrupt pending 0 ADC14IFG2_1 Interrupt pending 1 ADC14IFG20 ADC14MEM20 interrupt flag 20 1 read-only ADC14IFG20_enum_read read ADC14IFG20_0 No interrupt pending 0 ADC14IFG20_1 Interrupt pending 1 ADC14IFG21 ADC14MEM21 interrupt flag 21 1 read-only ADC14IFG21_enum_read read ADC14IFG21_0 No interrupt pending 0 ADC14IFG21_1 Interrupt pending 1 ADC14IFG22 ADC14MEM22 interrupt flag 22 1 read-only ADC14IFG22_enum_read read ADC14IFG22_0 No interrupt pending 0 ADC14IFG22_1 Interrupt pending 1 ADC14IFG23 ADC14MEM23 interrupt flag 23 1 read-only ADC14IFG23_enum_read read ADC14IFG23_0 No interrupt pending 0 ADC14IFG23_1 Interrupt pending 1 ADC14IFG24 ADC14MEM24 interrupt flag 24 1 read-only ADC14IFG24_enum_read read ADC14IFG24_0 No interrupt pending 0 ADC14IFG24_1 Interrupt pending 1 ADC14IFG25 ADC14MEM25 interrupt flag 25 1 read-only ADC14IFG25_enum_read read ADC14IFG25_0 No interrupt pending 0 ADC14IFG25_1 Interrupt pending 1 ADC14IFG26 ADC14MEM26 interrupt flag 26 1 read-only ADC14IFG26_enum_read read ADC14IFG26_0 No interrupt pending 0 ADC14IFG26_1 Interrupt pending 1 ADC14IFG27 ADC14MEM27 interrupt flag 27 1 read-only ADC14IFG27_enum_read read ADC14IFG27_0 No interrupt pending 0 ADC14IFG27_1 Interrupt pending 1 ADC14IFG28 ADC14MEM28 interrupt flag 28 1 read-only ADC14IFG28_enum_read read ADC14IFG28_0 No interrupt pending 0 ADC14IFG28_1 Interrupt pending 1 ADC14IFG29 ADC14MEM29 interrupt flag 29 1 read-only ADC14IFG29_enum_read read ADC14IFG29_0 No interrupt pending 0 ADC14IFG29_1 Interrupt pending 1 ADC14IFG3 ADC14MEM3 interrupt flag 3 1 read-only ADC14IFG3_enum_read read ADC14IFG3_0 No interrupt pending 0 ADC14IFG3_1 Interrupt pending 1 ADC14IFG30 ADC14MEM30 interrupt flag 30 1 read-only ADC14IFG30_enum_read read ADC14IFG30_0 No interrupt pending 0 ADC14IFG30_1 Interrupt pending 1 ADC14IFG31 ADC14MEM31 interrupt flag 31 1 read-only ADC14IFG31_enum_read read ADC14IFG31_0 No interrupt pending 0 ADC14IFG31_1 Interrupt pending 1 ADC14IFG4 ADC14MEM4 interrupt flag 4 1 read-only ADC14IFG4_enum_read read ADC14IFG4_0 No interrupt pending 0 ADC14IFG4_1 Interrupt pending 1 ADC14IFG5 ADC14MEM5 interrupt flag 5 1 read-only ADC14IFG5_enum_read read ADC14IFG5_0 No interrupt pending 0 ADC14IFG5_1 Interrupt pending 1 ADC14IFG6 ADC14MEM6 interrupt flag 6 1 read-only ADC14IFG6_enum_read read ADC14IFG6_0 No interrupt pending 0 ADC14IFG6_1 Interrupt pending 1 ADC14IFG7 ADC14MEM7 interrupt flag 7 1 read-only ADC14IFG7_enum_read read ADC14IFG7_0 No interrupt pending 0 ADC14IFG7_1 Interrupt pending 1 ADC14IFG8 ADC14MEM8 interrupt flag 8 1 read-only ADC14IFG8_enum_read read ADC14IFG8_0 No interrupt pending 0 ADC14IFG8_1 Interrupt pending 1 ADC14IFG9 ADC14MEM9 interrupt flag 9 1 read-only ADC14IFG9_enum_read read ADC14IFG9_0 No interrupt pending 0 ADC14IFG9_1 Interrupt pending 1 ADC14IFGR1 IFGR1 Interrupt Flag 1 Register 0x148 32 read-only n 0x0 0xFFFFFFFF ADC14HIIFG Interrupt flag for ADC14MEMx above comparator window 3 1 read-only ADC14HIIFG_enum_read read ADC14HIIFG_0 No interrupt pending 0 ADC14HIIFG_1 Interrupt pending 1 ADC14INIFG Interrupt flag for ADC14MEMx within comparator window 1 1 read-only ADC14INIFG_enum_read read ADC14INIFG_0 No interrupt pending 0 ADC14INIFG_1 Interrupt pending 1 ADC14LOIFG Interrupt flag for ADC14MEMx below comparator window 2 1 read-only ADC14LOIFG_enum_read read ADC14LOIFG_0 No interrupt pending 0 ADC14LOIFG_1 Interrupt pending 1 ADC14OVIFG ADC14MEMx overflow interrupt flag 4 1 read-only ADC14OVIFG_enum_read read ADC14OVIFG_0 No interrupt pending 0 ADC14OVIFG_1 Interrupt pending 1 ADC14RDYIFG ADC14 local buffered reference ready interrupt flag 6 1 read-only ADC14RDYIFG_enum_read read ADC14RDYIFG_0 No interrupt pending 0 ADC14RDYIFG_1 Interrupt pending 1 ADC14TOVIFG ADC14 conversion time overflow interrupt flag 5 1 read-only ADC14TOVIFG_enum_read read ADC14TOVIFG_0 No interrupt pending 0 ADC14TOVIFG_1 Interrupt pending 1 ADC14IV IV Interrupt Vector Register 0x154 32 read-write n 0x0 0xFFFFFFFF ADC14IV ADC14 interrupt vector value 0 32 read-write ADC14IV_0 No interrupt pending 0 ADC14IV_10 Interrupt Source: ADC14 in-window interrupt flag Interrupt Flag: ADC14INIFG 10 ADC14IV_12 Interrupt Source: ADC14MEM0 interrupt flag Interrupt Flag: ADC14IFG0 12 ADC14IV_14 Interrupt Source: ADC14MEM1 interrupt flag Interrupt Flag: ADC14IFG1 14 ADC14IV_16 Interrupt Source: ADC14MEM2 interrupt flag Interrupt Flag: ADC14IFG2 16 ADC14IV_18 Interrupt Source: ADC14MEM3 interrupt flag Interrupt Flag: ADC14IFG3 18 ADC14IV_2 Interrupt Source: ADC14MEMx overflow Interrupt Flag: ADC14OVIFG Interrupt Priority: Highest 2 ADC14IV_20 Interrupt Source: ADC14MEM4 interrupt flag Interrupt Flag: ADC14IFG4 20 ADC14IV_22 Interrupt Source: ADC14MEM5 interrupt flag Interrupt Flag: ADC14IFG5 22 ADC14IV_24 Interrupt Source: ADC14MEM6 interrupt flag Interrupt Flag: ADC14IFG6 24 ADC14IV_26 Interrupt Source: ADC14MEM7 interrupt flag Interrupt Flag: ADC14IFG7 26 ADC14IV_28 Interrupt Source: ADC14MEM8 interrupt flag Interrupt Flag: ADC14IFG8 28 ADC14IV_30 Interrupt Source: ADC14MEM9 interrupt flag Interrupt Flag: ADC14IFG9 30 ADC14IV_32 Interrupt Source: ADC14MEM10 interrupt flag Interrupt Flag: ADC14IFG10 32 ADC14IV_34 Interrupt Source: ADC14MEM11 interrupt flag Interrupt Flag: ADC14IFG11 34 ADC14IV_36 Interrupt Source: ADC14MEM12 interrupt flag Interrupt Flag: ADC14IFG12 36 ADC14IV_38 Interrupt Source: ADC14MEM13 interrupt flag Interrupt Flag: ADC14IFG13 38 ADC14IV_4 Interrupt Source: Conversion time overflow Interrupt Flag: ADC14TOVIFG 4 ADC14IV_40 Interrupt Source: ADC14MEM14 interrupt flag Interrupt Flag: ADC14IFG14 40 ADC14IV_42 Interrupt Source: ADC14MEM15 interrupt flag Interrupt Flag: ADC14IFG15 42 ADC14IV_44 Interrupt Source: ADC14MEM16 interrupt flag Interrupt Flag: ADC14IFG16 44 ADC14IV_46 Interrupt Source: ADC14MEM17 interrupt flag Interrupt Flag: ADC14IFG17 46 ADC14IV_48 Interrupt Source: ADC14MEM18 interrupt flag Interrupt Flag: ADC14IFG18 48 ADC14IV_50 Interrupt Source: ADC14MEM19 interrupt flag Interrupt Flag: ADC14IFG19 50 ADC14IV_52 Interrupt Source: ADC14MEM20 interrupt flag Interrupt Flag: ADC14IFG20 52 ADC14IV_54 Interrupt Source: ADC14MEM22 interrupt flag Interrupt Flag: ADC14IFG22 54 ADC14IV_56 Interrupt Source: ADC14MEM22 interrupt flag Interrupt Flag: ADC14IFG22 56 ADC14IV_58 Interrupt Source: ADC14MEM23 interrupt flag Interrupt Flag: ADC14IFG23 58 ADC14IV_6 Interrupt Source: ADC14 window high interrupt flag Interrupt Flag: ADC14HIIFG 6 ADC14IV_60 Interrupt Source: ADC14MEM24 interrupt flag Interrupt Flag: ADC14IFG24 60 ADC14IV_62 Interrupt Source: ADC14MEM25 interrupt flag Interrupt Flag: ADC14IFG25 62 ADC14IV_64 Interrupt Source: ADC14MEM26 interrupt flag Interrupt Flag: ADC14IFG26 64 ADC14IV_66 Interrupt Source: ADC14MEM27 interrupt flag Interrupt Flag: ADC14IFG27 66 ADC14IV_68 Interrupt Source: ADC14MEM28 interrupt flag Interrupt Flag: ADC14IFG28 68 ADC14IV_70 Interrupt Source: ADC14MEM29 interrupt flag Interrupt Flag: ADC14IFG29 70 ADC14IV_72 Interrupt Source: ADC14MEM30 interrupt flag Interrupt Flag: ADC14IFG30 72 ADC14IV_74 Interrupt Source: ADC14MEM31 interrupt flag Interrupt Flag: ADC14IFG31 74 ADC14IV_76 Interrupt Source: ADC14RDYIFG interrupt flag Interrupt Flag: ADC14RDYIFG Interrupt Priority: Lowest 76 ADC14IV_8 Interrupt Source: ADC14 window low interrupt flag Interrupt Flag: ADC14LOIFG 8 ADC14LO0 LO0 Window Comparator Low Threshold 0 Register 0x8 32 read-write n 0x0 0xFFFFFFFF ADC14LO0 Low threshold 0 0 16 read-write ADC14LO1 LO1 Window Comparator Low Threshold 1 Register 0x10 32 read-write n 0x0 0xFFFFFFFF ADC14LO1 Low threshold 1 0 16 read-write ADC14MCTL0 MCTL0 Conversion Memory Control Register 0x18 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL1 MCTL1 Conversion Memory Control Register 0x1C 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL10 MCTL10 Conversion Memory Control Register 0x40 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL11 MCTL11 Conversion Memory Control Register 0x44 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL12 MCTL12 Conversion Memory Control Register 0x48 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL13 MCTL13 Conversion Memory Control Register 0x4C 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL14 MCTL14 Conversion Memory Control Register 0x50 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL15 MCTL15 Conversion Memory Control Register 0x54 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL16 MCTL16 Conversion Memory Control Register 0x58 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL17 MCTL17 Conversion Memory Control Register 0x5C 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL18 MCTL18 Conversion Memory Control Register 0x60 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL19 MCTL19 Conversion Memory Control Register 0x64 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL2 MCTL2 Conversion Memory Control Register 0x20 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL20 MCTL20 Conversion Memory Control Register 0x68 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL21 MCTL21 Conversion Memory Control Register 0x6C 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL22 MCTL22 Conversion Memory Control Register 0x70 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL23 MCTL23 Conversion Memory Control Register 0x74 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL24 MCTL24 Conversion Memory Control Register 0x78 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL25 MCTL25 Conversion Memory Control Register 0x7C 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL26 MCTL26 Conversion Memory Control Register 0x80 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL27 MCTL27 Conversion Memory Control Register 0x84 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL28 MCTL28 Conversion Memory Control Register 0x88 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL29 MCTL29 Conversion Memory Control Register 0x8C 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL3 MCTL3 Conversion Memory Control Register 0x24 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL30 MCTL30 Conversion Memory Control Register 0x90 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL31 MCTL31 Conversion Memory Control Register 0x94 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL4 MCTL4 Conversion Memory Control Register 0x28 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL5 MCTL5 Conversion Memory Control Register 0x2C 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL6 MCTL6 Conversion Memory Control Register 0x30 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL7 MCTL7 Conversion Memory Control Register 0x34 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL8 MCTL8 Conversion Memory Control Register 0x38 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL9 MCTL9 Conversion Memory Control Register 0x3C 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1 If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11 If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13 If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15 If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17 If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19 If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21 If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23 If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25 If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27 If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29 If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3 If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31 If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5 If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7 If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9 If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[0] MCTL[%s] Conversion Memory Control Register 0x30 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[10] MCTL[%s] Conversion Memory Control Register 0x1FC 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[11] MCTL[%s] Conversion Memory Control Register 0x240 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[12] MCTL[%s] Conversion Memory Control Register 0x288 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[13] MCTL[%s] Conversion Memory Control Register 0x2D4 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[14] MCTL[%s] Conversion Memory Control Register 0x324 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[15] MCTL[%s] Conversion Memory Control Register 0x378 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[16] MCTL[%s] Conversion Memory Control Register 0x3D0 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[17] MCTL[%s] Conversion Memory Control Register 0x42C 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[18] MCTL[%s] Conversion Memory Control Register 0x48C 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[19] MCTL[%s] Conversion Memory Control Register 0x4F0 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[1] MCTL[%s] Conversion Memory Control Register 0x4C 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[20] MCTL[%s] Conversion Memory Control Register 0x558 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[21] MCTL[%s] Conversion Memory Control Register 0x5C4 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[22] MCTL[%s] Conversion Memory Control Register 0x634 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[23] MCTL[%s] Conversion Memory Control Register 0x6A8 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[24] MCTL[%s] Conversion Memory Control Register 0x720 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[25] MCTL[%s] Conversion Memory Control Register 0x79C 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[26] MCTL[%s] Conversion Memory Control Register 0x81C 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[27] MCTL[%s] Conversion Memory Control Register 0x8A0 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[28] MCTL[%s] Conversion Memory Control Register 0x928 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[29] MCTL[%s] Conversion Memory Control Register 0x9B4 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[2] MCTL[%s] Conversion Memory Control Register 0x6C 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[30] MCTL[%s] Conversion Memory Control Register 0xA44 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[31] MCTL[%s] Conversion Memory Control Register 0xAD8 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[3] MCTL[%s] Conversion Memory Control Register 0x90 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[4] MCTL[%s] Conversion Memory Control Register 0xB8 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[5] MCTL[%s] Conversion Memory Control Register 0xE4 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[6] MCTL[%s] Conversion Memory Control Register 0x114 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[7] MCTL[%s] Conversion Memory Control Register 0x148 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[8] MCTL[%s] Conversion Memory Control Register 0x180 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MCTL[9] MCTL[%s] Conversion Memory Control Register 0x1BC 32 read-write n 0x0 0xFFFFFFFF ADC14DIF Differential mode 13 1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14EOS End of sequence 7 1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14INCH Input channel select 0 5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 8 4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14WINC Comparator window enable 14 1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 15 1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 ADC14MEM0 MEM0 Conversion Memory Register 0x98 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM1 MEM1 Conversion Memory Register 0x9C 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM10 MEM10 Conversion Memory Register 0xC0 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM11 MEM11 Conversion Memory Register 0xC4 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM12 MEM12 Conversion Memory Register 0xC8 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM13 MEM13 Conversion Memory Register 0xCC 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM14 MEM14 Conversion Memory Register 0xD0 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM15 MEM15 Conversion Memory Register 0xD4 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM16 MEM16 Conversion Memory Register 0xD8 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM17 MEM17 Conversion Memory Register 0xDC 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM18 MEM18 Conversion Memory Register 0xE0 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM19 MEM19 Conversion Memory Register 0xE4 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM2 MEM2 Conversion Memory Register 0xA0 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM20 MEM20 Conversion Memory Register 0xE8 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM21 MEM21 Conversion Memory Register 0xEC 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM22 MEM22 Conversion Memory Register 0xF0 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM23 MEM23 Conversion Memory Register 0xF4 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM24 MEM24 Conversion Memory Register 0xF8 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM25 MEM25 Conversion Memory Register 0xFC 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM26 MEM26 Conversion Memory Register 0x100 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM27 MEM27 Conversion Memory Register 0x104 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM28 MEM28 Conversion Memory Register 0x108 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM29 MEM29 Conversion Memory Register 0x10C 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM3 MEM3 Conversion Memory Register 0xA4 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM30 MEM30 Conversion Memory Register 0x110 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM31 MEM31 Conversion Memory Register 0x114 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM4 MEM4 Conversion Memory Register 0xA8 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM5 MEM5 Conversion Memory Register 0xAC 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM6 MEM6 Conversion Memory Register 0xB0 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM7 MEM7 Conversion Memory Register 0xB4 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM8 MEM8 Conversion Memory Register 0xB8 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM9 MEM9 Conversion Memory Register 0xBC 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[0] MEM[%s] Conversion Memory Register 0x130 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[10] MEM[%s] Conversion Memory Register 0x7FC 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[11] MEM[%s] Conversion Memory Register 0x8C0 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[12] MEM[%s] Conversion Memory Register 0x988 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[13] MEM[%s] Conversion Memory Register 0xA54 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[14] MEM[%s] Conversion Memory Register 0xB24 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[15] MEM[%s] Conversion Memory Register 0xBF8 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[16] MEM[%s] Conversion Memory Register 0xCD0 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[17] MEM[%s] Conversion Memory Register 0xDAC 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[18] MEM[%s] Conversion Memory Register 0xE8C 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[19] MEM[%s] Conversion Memory Register 0xF70 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[1] MEM[%s] Conversion Memory Register 0x1CC 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[20] MEM[%s] Conversion Memory Register 0x1058 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[21] MEM[%s] Conversion Memory Register 0x1144 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[22] MEM[%s] Conversion Memory Register 0x1234 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[23] MEM[%s] Conversion Memory Register 0x1328 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[24] MEM[%s] Conversion Memory Register 0x1420 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[25] MEM[%s] Conversion Memory Register 0x151C 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[26] MEM[%s] Conversion Memory Register 0x161C 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[27] MEM[%s] Conversion Memory Register 0x1720 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[28] MEM[%s] Conversion Memory Register 0x1828 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[29] MEM[%s] Conversion Memory Register 0x1934 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[2] MEM[%s] Conversion Memory Register 0x26C 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[30] MEM[%s] Conversion Memory Register 0x1A44 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[31] MEM[%s] Conversion Memory Register 0x1B58 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[3] MEM[%s] Conversion Memory Register 0x310 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[4] MEM[%s] Conversion Memory Register 0x3B8 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[5] MEM[%s] Conversion Memory Register 0x464 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[6] MEM[%s] Conversion Memory Register 0x514 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[7] MEM[%s] Conversion Memory Register 0x5C8 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[8] MEM[%s] Conversion Memory Register 0x680 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write ADC14MEM[9] MEM[%s] Conversion Memory Register 0x73C 32 read-write n 0x0 0x0 Conversion_Results Conversion Result 0 16 read-write AES256 AES256 AES256 0x40003C00 0x0 0x10 registers n AES256_IRQ AES256 Interrupt 28 AESACTL0 CTL0 AES Accelerator Control Register 0 0x0 16 read-write n 0x0 0xFFFF AESCMEN AES cipher mode enable 15 1 read-write AESCMEN_0 No DMA triggers are generated 0 AESCMEN_1 DMA ciphermode support operation is enabled and the corresponding DMA triggers are generated 1 AESCMx AES cipher mode select 5 2 read-write AESCMx_0 ECB 0 AESCMx_1 CBC 1 AESCMx_2 OFB 2 AESCMx_3 CFB 3 AESERRFG AES error flag 11 1 read-write AESERRFG_0 No error 0 AESERRFG_1 Error occurred 1 AESKLx AES key length 2 2 read-write AESKLx_0 AES128. The key size is 128 bit 0 AESKLx_1 AES192. The key size is 192 bit. 1 AESKLx_2 AES256. The key size is 256 bit 2 AESOPx AES operation 0 2 read-write AESOPx_0 Encryption 0 AESOPx_1 Decryption. The provided key is the same key used for encryption 1 AESOPx_2 Generate first round key required for decryption 2 AESOPx_3 Decryption. The provided key is the first round key required for decryption 3 AESRDYIE AES ready interrupt enable 12 1 read-write AESRDYIE_0 Interrupt disabled 0 AESRDYIE_1 Interrupt enabled 1 AESRDYIFG AES ready interrupt flag 8 1 read-write AESRDYIFG_0 No interrupt pending 0 AESRDYIFG_1 Interrupt pending 1 AESSWRST AES software reset 7 1 read-write AESSWRST_0 No reset 0 AESSWRST_1 Reset AES accelerator module 1 AESACTL1 CTL1 AES Accelerator Control Register 1 0x2 16 read-write n 0x0 0xFFFF AESBLKCNTx Cipher Block Counter 0 8 read-write AESADIN DIN AES Accelerator Data In Register 0x8 16 write-only n 0x0 0xFFFF AESDIN0x AES data in byte n when AESADIN is written as half-word 0 8 write-only AESDIN1x AES data in byte n+1 when AESADIN is written as half-word 8 8 write-only AESADOUT DOUT AES Accelerator Data Out Register 0xA 16 write-only n 0x0 0xFFFF AESDOUT0x AES data out byte n when AESADOUT is read as half-word 0 8 write-only AESDOUT1x AES data out byte n+1 when AESADOUT is read as half-word 8 8 write-only AESAKEY KEY AES Accelerator Key Register 0x6 16 write-only n 0x0 0xFFFF AESKEY0x AES key byte n when AESAKEY is written as half-word 0 8 write-only AESKEY1x AES key byte n+1 when AESAKEY is written as half-word 8 8 write-only AESASTAT STAT AES Accelerator Status Register 0x4 16 read-write n 0x0 0xFFFF AESBUSY AES accelerator module busy 0 1 read-write AESBUSY_0 Not busy 0 AESBUSY_1 Busy 1 AESDINCNTx Bytes written via AESADIN, AESAXDIN or AESAXIN 8 4 read-only AESDINWR All 16 bytes written to AESADIN, AESAXDIN or AESAXIN 2 1 read-write AESDINWR_0 Not all bytes written 0 AESDINWR_1 All bytes written 1 AESDOUTCNTx Bytes read via AESADOUT 12 4 read-only AESDOUTRD All 16 bytes read from AESADOUT 3 1 read-only AESDOUTRD_enum_read read AESDOUTRD_0 Not all bytes read 0 AESDOUTRD_1 All bytes read 1 AESKEYCNTx Bytes written via AESAKEY for AESKLx=00, half-words written via AESAKEY 4 4 read-only AESKEYWR All 16 bytes written to AESAKEY 1 1 read-write AESKEYWR_0 Not all bytes written 0 AESKEYWR_1 All bytes written 1 AESAXDIN XDIN AES Accelerator XORed Data In Register 0xC 16 write-only n 0x0 0xFFFF AESXDIN0x AES data in byte n when AESAXDIN is written as half-word 0 8 write-only AESXDIN1x AES data in byte n+1 when AESAXDIN is written as half-word 8 8 write-only AESAXIN XIN AES Accelerator XORed Data In Register 0xE 16 write-only n 0x0 0xFFFF AESXIN0x AES data in byte n when AESAXIN is written as half-word 0 8 write-only AESXIN1x AES data in byte n+1 when AESAXIN is written as half-word 8 8 write-only CAPTIO0 CAPTIO0 CAPTIO0 0x40005400 0x0 0x10 registers n CAPTIOxCTL CTL Capacitive Touch IO x Control Register 0xE 16 read-write n 0x0 0xFFFF CAPTIOEN Capacitive Touch IO enable 8 1 read-write CAPTIOEN_0 All Capacitive Touch IOs are disabled. Signal towards timers is 0. 0 CAPTIOEN_1 Selected Capacitive Touch IO is enabled 1 CAPTIOPISELx Capacitive Touch IO pin select 1 3 read-write CAPTIOPISELx_0 Px.0 0 CAPTIOPISELx_1 Px.1 1 CAPTIOPISELx_2 Px.2 2 CAPTIOPISELx_3 Px.3 3 CAPTIOPISELx_4 Px.4 4 CAPTIOPISELx_5 Px.5 5 CAPTIOPISELx_6 Px.6 6 CAPTIOPISELx_7 Px.7 7 CAPTIOPOSELx Capacitive Touch IO port select 4 4 read-write CAPTIOPOSELx_0 Px = PJ 0 CAPTIOPOSELx_1 Px = P1 1 CAPTIOPOSELx_10 Px = P10 10 CAPTIOPOSELx_11 Px = P11 11 CAPTIOPOSELx_12 Px = P12 12 CAPTIOPOSELx_13 Px = P13 13 CAPTIOPOSELx_14 Px = P14 14 CAPTIOPOSELx_15 Px = P15 15 CAPTIOPOSELx_2 Px = P2 2 CAPTIOPOSELx_3 Px = P3 3 CAPTIOPOSELx_4 Px = P4 4 CAPTIOPOSELx_5 Px = P5 5 CAPTIOPOSELx_6 Px = P6 6 CAPTIOPOSELx_7 Px = P7 7 CAPTIOPOSELx_8 Px = P8 8 CAPTIOPOSELx_9 Px = P9 9 CAPTIOSTATE Capacitive Touch IO state 9 1 read-only CAPTIOSTATE_enum_read read CAPTIOSTATE_0 Curent state 0 or Capacitive Touch IO is disabled 0 CAPTIOSTATE_1 Current state 1 1 CAPTIO1 CAPTIO1 CAPTIO1 0x40005800 0x0 0x10 registers n CAPTIOxCTL CTL Capacitive Touch IO x Control Register 0xE 16 read-write n 0x0 0xFFFF CAPTIOEN Capacitive Touch IO enable 8 1 read-write CAPTIOEN_0 All Capacitive Touch IOs are disabled. Signal towards timers is 0. 0 CAPTIOEN_1 Selected Capacitive Touch IO is enabled 1 CAPTIOPISELx Capacitive Touch IO pin select 1 3 read-write CAPTIOPISELx_0 Px.0 0 CAPTIOPISELx_1 Px.1 1 CAPTIOPISELx_2 Px.2 2 CAPTIOPISELx_3 Px.3 3 CAPTIOPISELx_4 Px.4 4 CAPTIOPISELx_5 Px.5 5 CAPTIOPISELx_6 Px.6 6 CAPTIOPISELx_7 Px.7 7 CAPTIOPOSELx Capacitive Touch IO port select 4 4 read-write CAPTIOPOSELx_0 Px = PJ 0 CAPTIOPOSELx_1 Px = P1 1 CAPTIOPOSELx_10 Px = P10 10 CAPTIOPOSELx_11 Px = P11 11 CAPTIOPOSELx_12 Px = P12 12 CAPTIOPOSELx_13 Px = P13 13 CAPTIOPOSELx_14 Px = P14 14 CAPTIOPOSELx_15 Px = P15 15 CAPTIOPOSELx_2 Px = P2 2 CAPTIOPOSELx_3 Px = P3 3 CAPTIOPOSELx_4 Px = P4 4 CAPTIOPOSELx_5 Px = P5 5 CAPTIOPOSELx_6 Px = P6 6 CAPTIOPOSELx_7 Px = P7 7 CAPTIOPOSELx_8 Px = P8 8 CAPTIOPOSELx_9 Px = P9 9 CAPTIOSTATE Capacitive Touch IO state 9 1 read-only CAPTIOSTATE_enum_read read CAPTIOSTATE_0 Curent state 0 or Capacitive Touch IO is disabled 0 CAPTIOSTATE_1 Current state 1 1 COMP_E0 COMP_E0 COMP_E0 0x40003400 0x0 0x10 registers n COMP_E0_IRQ COMP_E0 Interrupt 6 CExCTL0 CTL0 Comparator Control Register 0 0x0 16 read-write n 0x0 0xFFFF CEIMEN Channel input enable for the - terminal 15 1 read-write CEIMEN_0 Selected analog input channel for V- terminal is disabled 0 CEIMEN_1 Selected analog input channel for V- terminal is enabled 1 CEIMSEL Channel input selected for the - terminal 8 4 read-write CEIMSEL_0 Channel 0 selected 0 CEIMSEL_1 Channel 1 selected 1 CEIMSEL_10 Channel 10 selected 10 CEIMSEL_11 Channel 11 selected 11 CEIMSEL_12 Channel 12 selected 12 CEIMSEL_13 Channel 13 selected 13 CEIMSEL_14 Channel 14 selected 14 CEIMSEL_15 Channel 15 selected 15 CEIMSEL_2 Channel 2 selected 2 CEIMSEL_3 Channel 3 selected 3 CEIMSEL_4 Channel 4 selected 4 CEIMSEL_5 Channel 5 selected 5 CEIMSEL_6 Channel 6 selected 6 CEIMSEL_7 Channel 7 selected 7 CEIMSEL_8 Channel 8 selected 8 CEIMSEL_9 Channel 9 selected 9 CEIPEN Channel input enable for the V+ terminal 7 1 read-write CEIPEN_0 Selected analog input channel for V+ terminal is disabled 0 CEIPEN_1 Selected analog input channel for V+ terminal is enabled 1 CEIPSEL Channel input selected for the V+ terminal 0 4 read-write CEIPSEL_0 Channel 0 selected 0 CEIPSEL_1 Channel 1 selected 1 CEIPSEL_10 Channel 10 selected 10 CEIPSEL_11 Channel 11 selected 11 CEIPSEL_12 Channel 12 selected 12 CEIPSEL_13 Channel 13 selected 13 CEIPSEL_14 Channel 14 selected 14 CEIPSEL_15 Channel 15 selected 15 CEIPSEL_2 Channel 2 selected 2 CEIPSEL_3 Channel 3 selected 3 CEIPSEL_4 Channel 4 selected 4 CEIPSEL_5 Channel 5 selected 5 CEIPSEL_6 Channel 6 selected 6 CEIPSEL_7 Channel 7 selected 7 CEIPSEL_8 Channel 8 selected 8 CEIPSEL_9 Channel 9 selected 9 CExCTL1 CTL1 Comparator Control Register 1 0x2 16 read-write n 0x0 0xFFFF CEEX Exchange 5 1 read-write CEF Comparator output filter 2 1 read-write CEF_0 Comparator output is not filtered 0 CEF_1 Comparator output is filtered 1 CEFDLY Filter delay 6 2 read-write CEFDLY_0 Typical filter delay of TBD (450) ns 0 CEFDLY_1 Typical filter delay of TBD (900) ns 1 CEFDLY_2 Typical filter delay of TBD (1800) ns 2 CEFDLY_3 Typical filter delay of TBD (3600) ns 3 CEIES Interrupt edge select for CEIIFG and CEIFG 3 1 read-write CEIES_0 Rising edge for CEIFG, falling edge for CEIIFG 0 CEIES_1 Falling edge for CEIFG, rising edge for CEIIFG 1 CEMRVL This bit is valid of CEMRVS is set to 1 11 1 read-write CEMRVL_0 VREF0 is selected if CERS = 00, 01, or 10 0 CEMRVL_1 VREF1 is selected if CERS = 00, 01, or 10 1 CEMRVS This bit defines if the comparator output selects between VREF0 or VREF1 if CERS = 00, 01, or 10. 12 1 read-write CEMRVS_0 Comparator output state selects between VREF0 or VREF1 0 CEMRVS_1 CEMRVL selects between VREF0 or VREF1 1 CEON Comparator On 10 1 read-write CEON_0 Off 0 CEON_1 On 1 CEOUT Comparator output value 0 1 read-write CEOUTPOL Comparator output polarity 1 1 read-write CEOUTPOL_0 Noninverted 0 CEOUTPOL_1 Inverted 1 CEPWRMD Power Mode 8 2 read-write CEPWRMD_0 High-speed mode 0 CEPWRMD_1 Normal mode 1 CEPWRMD_2 Ultra-low power mode 2 CESHORT Input short 4 1 read-write CESHORT_0 Inputs not shorted 0 CESHORT_1 Inputs shorted 1 CExCTL2 CTL2 Comparator Control Register 2 0x4 16 read-write n 0x0 0xFFFF CEREF0 Reference resistor tap 0 0 5 read-write CEREF1 Reference resistor tap 1 8 5 read-write CEREFACC Reference accuracy 15 1 read-write CEREFACC_0 Static mode 0 CEREFACC_1 Clocked (low power, low accuracy) mode 1 CEREFL Reference voltage level 13 2 read-write CEREFL_0 Reference amplifier is disabled. No reference voltage is requested 0 CEREFL_1 1.2 V is selected as shared reference voltage input 1 CEREFL_2 2.0 V is selected as shared reference voltage input 2 CEREFL_3 2.5 V is selected as shared reference voltage input 3 CERS Reference source 6 2 read-write CERS_0 No current is drawn by the reference circuitry 0 CERS_1 VCC applied to the resistor ladder 1 CERS_2 Shared reference voltage applied to the resistor ladder 2 CERS_3 Shared reference voltage supplied to V(CREF). Resistor ladder is off 3 CERSEL Reference select 5 1 read-write CERSEL_0 When CEEX = 0, VREF is applied to the V+ terminal When CEEX = 1, VREF is applied to the V- terminal 0 CERSEL_1 When CEEX = 0, VREF is applied to the V- terminal When CEEX = 1, VREF is applied to the V+ terminal 1 CExCTL3 CTL3 Comparator Control Register 3 0x6 16 read-write n 0x0 0xFFFF CEPD0 Port disable 0 1 read-write CEPD0_0 The input buffer is enabled 0 CEPD0_1 The input buffer is disabled 1 CEPD1 Port disable 1 1 read-write CEPD1_0 The input buffer is enabled 0 CEPD1_1 The input buffer is disabled 1 CEPD10 Port disable 10 1 read-write CEPD10_0 The input buffer is enabled 0 CEPD10_1 The input buffer is disabled 1 CEPD11 Port disable 11 1 read-write CEPD11_0 The input buffer is enabled 0 CEPD11_1 The input buffer is disabled 1 CEPD12 Port disable 12 1 read-write CEPD12_0 The input buffer is enabled 0 CEPD12_1 The input buffer is disabled 1 CEPD13 Port disable 13 1 read-write CEPD13_0 The input buffer is enabled 0 CEPD13_1 The input buffer is disabled 1 CEPD14 Port disable 14 1 read-write CEPD14_0 The input buffer is enabled 0 CEPD14_1 The input buffer is disabled 1 CEPD15 Port disable 15 1 read-write CEPD15_0 The input buffer is enabled 0 CEPD15_1 The input buffer is disabled 1 CEPD2 Port disable 2 1 read-write CEPD2_0 The input buffer is enabled 0 CEPD2_1 The input buffer is disabled 1 CEPD3 Port disable 3 1 read-write CEPD3_0 The input buffer is enabled 0 CEPD3_1 The input buffer is disabled 1 CEPD4 Port disable 4 1 read-write CEPD4_0 The input buffer is enabled 0 CEPD4_1 The input buffer is disabled 1 CEPD5 Port disable 5 1 read-write CEPD5_0 The input buffer is enabled 0 CEPD5_1 The input buffer is disabled 1 CEPD6 Port disable 6 1 read-write CEPD6_0 The input buffer is enabled 0 CEPD6_1 The input buffer is disabled 1 CEPD7 Port disable 7 1 read-write CEPD7_0 The input buffer is enabled 0 CEPD7_1 The input buffer is disabled 1 CEPD8 Port disable 8 1 read-write CEPD8_0 The input buffer is enabled 0 CEPD8_1 The input buffer is disabled 1 CEPD9 Port disable 9 1 read-write CEPD9_0 The input buffer is enabled 0 CEPD9_1 The input buffer is disabled 1 CExINT INT Comparator Interrupt Control Register 0xC 16 read-write n 0x0 0xFFFF CEIE Comparator output interrupt enable 8 1 read-write CEIE_0 Interrupt disabled 0 CEIE_1 Interrupt enabled 1 CEIFG Comparator output interrupt flag 0 1 read-write CEIFG_0 No interrupt pending 0 CEIFG_1 Interrupt pending 1 CEIIE Comparator output interrupt enable inverted polarity 9 1 read-write CEIIE_0 Interrupt disabled 0 CEIIE_1 Interrupt enabled 1 CEIIFG Comparator output inverted interrupt flag 1 1 read-write CEIIFG_0 No interrupt pending 0 CEIIFG_1 Interrupt pending 1 CERDYIE Comparator ready interrupt enable 12 1 read-write CERDYIE_0 Interrupt disabled 0 CERDYIE_1 Interrupt enabled 1 CERDYIFG Comparator ready interrupt flag 4 1 read-write CERDYIFG_0 No interrupt pending 0 CERDYIFG_1 Interrupt pending 1 CExIV IV Comparator Interrupt Vector Word Register 0xE 16 read-only n 0x0 0xFFFF CEIV Comparator interrupt vector word register 0 16 read-only CEIV_enum_read read CEIV_0 No interrupt pending 0 CEIV_10 Interrupt Source: Comparator ready interrupt Interrupt Flag: CERDYIFG Interrupt Priority: Lowest 10 CEIV_2 Interrupt Source: CEOUT interrupt Interrupt Flag: CEIFG Interrupt Priority: Highest 2 CEIV_4 Interrupt Source: CEOUT interrupt inverted polarity Interrupt Flag: CEIIFG 4 COMP_E1 COMP_E1 COMP_E1 0x40003800 0x0 0x10 registers n COMP_E1_IRQ COMP_E1 Interrupt 7 CExCTL0 CTL0 Comparator Control Register 0 0x0 16 read-write n 0x0 0xFFFF CEIMEN Channel input enable for the - terminal 15 1 read-write CEIMEN_0 Selected analog input channel for V- terminal is disabled 0 CEIMEN_1 Selected analog input channel for V- terminal is enabled 1 CEIMSEL Channel input selected for the - terminal 8 4 read-write CEIMSEL_0 Channel 0 selected 0 CEIMSEL_1 Channel 1 selected 1 CEIMSEL_10 Channel 10 selected 10 CEIMSEL_11 Channel 11 selected 11 CEIMSEL_12 Channel 12 selected 12 CEIMSEL_13 Channel 13 selected 13 CEIMSEL_14 Channel 14 selected 14 CEIMSEL_15 Channel 15 selected 15 CEIMSEL_2 Channel 2 selected 2 CEIMSEL_3 Channel 3 selected 3 CEIMSEL_4 Channel 4 selected 4 CEIMSEL_5 Channel 5 selected 5 CEIMSEL_6 Channel 6 selected 6 CEIMSEL_7 Channel 7 selected 7 CEIMSEL_8 Channel 8 selected 8 CEIMSEL_9 Channel 9 selected 9 CEIPEN Channel input enable for the V+ terminal 7 1 read-write CEIPEN_0 Selected analog input channel for V+ terminal is disabled 0 CEIPEN_1 Selected analog input channel for V+ terminal is enabled 1 CEIPSEL Channel input selected for the V+ terminal 0 4 read-write CEIPSEL_0 Channel 0 selected 0 CEIPSEL_1 Channel 1 selected 1 CEIPSEL_10 Channel 10 selected 10 CEIPSEL_11 Channel 11 selected 11 CEIPSEL_12 Channel 12 selected 12 CEIPSEL_13 Channel 13 selected 13 CEIPSEL_14 Channel 14 selected 14 CEIPSEL_15 Channel 15 selected 15 CEIPSEL_2 Channel 2 selected 2 CEIPSEL_3 Channel 3 selected 3 CEIPSEL_4 Channel 4 selected 4 CEIPSEL_5 Channel 5 selected 5 CEIPSEL_6 Channel 6 selected 6 CEIPSEL_7 Channel 7 selected 7 CEIPSEL_8 Channel 8 selected 8 CEIPSEL_9 Channel 9 selected 9 CExCTL1 CTL1 Comparator Control Register 1 0x2 16 read-write n 0x0 0xFFFF CEEX Exchange 5 1 read-write CEF Comparator output filter 2 1 read-write CEF_0 Comparator output is not filtered 0 CEF_1 Comparator output is filtered 1 CEFDLY Filter delay 6 2 read-write CEFDLY_0 Typical filter delay of TBD (450) ns 0 CEFDLY_1 Typical filter delay of TBD (900) ns 1 CEFDLY_2 Typical filter delay of TBD (1800) ns 2 CEFDLY_3 Typical filter delay of TBD (3600) ns 3 CEIES Interrupt edge select for CEIIFG and CEIFG 3 1 read-write CEIES_0 Rising edge for CEIFG, falling edge for CEIIFG 0 CEIES_1 Falling edge for CEIFG, rising edge for CEIIFG 1 CEMRVL This bit is valid of CEMRVS is set to 1 11 1 read-write CEMRVL_0 VREF0 is selected if CERS = 00, 01, or 10 0 CEMRVL_1 VREF1 is selected if CERS = 00, 01, or 10 1 CEMRVS This bit defines if the comparator output selects between VREF0 or VREF1 if CERS = 00, 01, or 10. 12 1 read-write CEMRVS_0 Comparator output state selects between VREF0 or VREF1 0 CEMRVS_1 CEMRVL selects between VREF0 or VREF1 1 CEON Comparator On 10 1 read-write CEON_0 Off 0 CEON_1 On 1 CEOUT Comparator output value 0 1 read-write CEOUTPOL Comparator output polarity 1 1 read-write CEOUTPOL_0 Noninverted 0 CEOUTPOL_1 Inverted 1 CEPWRMD Power Mode 8 2 read-write CEPWRMD_0 High-speed mode 0 CEPWRMD_1 Normal mode 1 CEPWRMD_2 Ultra-low power mode 2 CESHORT Input short 4 1 read-write CESHORT_0 Inputs not shorted 0 CESHORT_1 Inputs shorted 1 CExCTL2 CTL2 Comparator Control Register 2 0x4 16 read-write n 0x0 0xFFFF CEREF0 Reference resistor tap 0 0 5 read-write CEREF1 Reference resistor tap 1 8 5 read-write CEREFACC Reference accuracy 15 1 read-write CEREFACC_0 Static mode 0 CEREFACC_1 Clocked (low power, low accuracy) mode 1 CEREFL Reference voltage level 13 2 read-write CEREFL_0 Reference amplifier is disabled. No reference voltage is requested 0 CEREFL_1 1.2 V is selected as shared reference voltage input 1 CEREFL_2 2.0 V is selected as shared reference voltage input 2 CEREFL_3 2.5 V is selected as shared reference voltage input 3 CERS Reference source 6 2 read-write CERS_0 No current is drawn by the reference circuitry 0 CERS_1 VCC applied to the resistor ladder 1 CERS_2 Shared reference voltage applied to the resistor ladder 2 CERS_3 Shared reference voltage supplied to V(CREF). Resistor ladder is off 3 CERSEL Reference select 5 1 read-write CERSEL_0 When CEEX = 0, VREF is applied to the V+ terminal When CEEX = 1, VREF is applied to the V- terminal 0 CERSEL_1 When CEEX = 0, VREF is applied to the V- terminal When CEEX = 1, VREF is applied to the V+ terminal 1 CExCTL3 CTL3 Comparator Control Register 3 0x6 16 read-write n 0x0 0xFFFF CEPD0 Port disable 0 1 read-write CEPD0_0 The input buffer is enabled 0 CEPD0_1 The input buffer is disabled 1 CEPD1 Port disable 1 1 read-write CEPD1_0 The input buffer is enabled 0 CEPD1_1 The input buffer is disabled 1 CEPD10 Port disable 10 1 read-write CEPD10_0 The input buffer is enabled 0 CEPD10_1 The input buffer is disabled 1 CEPD11 Port disable 11 1 read-write CEPD11_0 The input buffer is enabled 0 CEPD11_1 The input buffer is disabled 1 CEPD12 Port disable 12 1 read-write CEPD12_0 The input buffer is enabled 0 CEPD12_1 The input buffer is disabled 1 CEPD13 Port disable 13 1 read-write CEPD13_0 The input buffer is enabled 0 CEPD13_1 The input buffer is disabled 1 CEPD14 Port disable 14 1 read-write CEPD14_0 The input buffer is enabled 0 CEPD14_1 The input buffer is disabled 1 CEPD15 Port disable 15 1 read-write CEPD15_0 The input buffer is enabled 0 CEPD15_1 The input buffer is disabled 1 CEPD2 Port disable 2 1 read-write CEPD2_0 The input buffer is enabled 0 CEPD2_1 The input buffer is disabled 1 CEPD3 Port disable 3 1 read-write CEPD3_0 The input buffer is enabled 0 CEPD3_1 The input buffer is disabled 1 CEPD4 Port disable 4 1 read-write CEPD4_0 The input buffer is enabled 0 CEPD4_1 The input buffer is disabled 1 CEPD5 Port disable 5 1 read-write CEPD5_0 The input buffer is enabled 0 CEPD5_1 The input buffer is disabled 1 CEPD6 Port disable 6 1 read-write CEPD6_0 The input buffer is enabled 0 CEPD6_1 The input buffer is disabled 1 CEPD7 Port disable 7 1 read-write CEPD7_0 The input buffer is enabled 0 CEPD7_1 The input buffer is disabled 1 CEPD8 Port disable 8 1 read-write CEPD8_0 The input buffer is enabled 0 CEPD8_1 The input buffer is disabled 1 CEPD9 Port disable 9 1 read-write CEPD9_0 The input buffer is enabled 0 CEPD9_1 The input buffer is disabled 1 CExINT INT Comparator Interrupt Control Register 0xC 16 read-write n 0x0 0xFFFF CEIE Comparator output interrupt enable 8 1 read-write CEIE_0 Interrupt disabled 0 CEIE_1 Interrupt enabled 1 CEIFG Comparator output interrupt flag 0 1 read-write CEIFG_0 No interrupt pending 0 CEIFG_1 Interrupt pending 1 CEIIE Comparator output interrupt enable inverted polarity 9 1 read-write CEIIE_0 Interrupt disabled 0 CEIIE_1 Interrupt enabled 1 CEIIFG Comparator output inverted interrupt flag 1 1 read-write CEIIFG_0 No interrupt pending 0 CEIIFG_1 Interrupt pending 1 CERDYIE Comparator ready interrupt enable 12 1 read-write CERDYIE_0 Interrupt disabled 0 CERDYIE_1 Interrupt enabled 1 CERDYIFG Comparator ready interrupt flag 4 1 read-write CERDYIFG_0 No interrupt pending 0 CERDYIFG_1 Interrupt pending 1 CExIV IV Comparator Interrupt Vector Word Register 0xE 16 read-only n 0x0 0xFFFF CEIV Comparator interrupt vector word register 0 16 read-only CEIV_enum_read read CEIV_0 No interrupt pending 0 CEIV_10 Interrupt Source: Comparator ready interrupt Interrupt Flag: CERDYIFG Interrupt Priority: Lowest 10 CEIV_2 Interrupt Source: CEOUT interrupt Interrupt Flag: CEIFG Interrupt Priority: Highest 2 CEIV_4 Interrupt Source: CEOUT interrupt inverted polarity Interrupt Flag: CEIIFG 4 CRC32 CRC32 CRC32 0x40004000 0x0 0x20 registers n CRC16DI CRC16DI Data Input for CRC16 computation 0x10 16 read-write n 0x0 0xFFFF CRC16DI CRC16 data in 0 16 read-write CRC16DIRB CRC16DIRB CRC16 Data In Reverse 0x14 16 read-write n 0x0 0xFFFF CRC16DIRB CRC16 data in reverse byte 0 16 read-write CRC16INIRES CRC16INIRES CRC16 Initialization and Result register 0x18 16 read-write n 0xFFFF 0xFFFF CRC16INIRES CRC16 initialization and result 0 16 read-write CRC16RESR CRC16RESR CRC16 Result Reverse 0x1E 16 read-write n 0xFFFF 0xFFFF CRC16RESR CRC16 reverse result 0 16 read-write CRC32DI CRC32DI Data Input for CRC32 Signature Computation 0x0 16 read-write n 0x0 0xFFFF CRC32DI Data input register 0 16 read-write CRC32DIRB CRC32DIRB Data In Reverse for CRC32 Computation 0x4 16 read-write n 0x0 0xFFFF CRC32DIRB Data input register reversed 0 16 read-write CRC32INIRES_HI CRC32INIRES_HI CRC32 Initialization and Result, upper 16 bits 0xA 16 read-write n 0x0 0xFFFF CRC32INIRES_HI CRC32 initialization and result, upper 16 bits 0 16 read-write CRC32INIRES_LO CRC32INIRES_LO CRC32 Initialization and Result, lower 16 bits 0x8 16 read-write n 0x0 0xFFFF CRC32INIRES_LO CRC32 initialization and result, lower 16 bits 0 16 read-write CRC32RESR_HI CRC32RESR_HI CRC32 Result Reverse, Upper 16 bits 0xE 16 read-write n 0xFFFF 0xFFFF CRC32RESR_HI CRC32 reverse result, upper 16 bits 0 16 read-write CRC32RESR_LO CRC32RESR_LO CRC32 Result Reverse, lower 16 bits 0xC 16 read-write n 0xFFFF 0xFFFF CRC32RESR_LO CRC32 reverse result, lower 16 bits 0 16 read-write CS CS CS 0x40010400 0x0 0x68 registers n CS_IRQ CS Interrupt 1 CSCLKEN CLKEN Clock Enable Register 0x30 32 read-write n 0xF 0xFFFF847F ACLK_EN ACLK system clock conditional request enable 0 1 read-write ACLK_EN_0 ACLK disabled regardless of conditional clock requests 0 ACLK_EN_1 ACLK enabled based on any conditional clock requests 1 HSMCLK_EN HSMCLK system clock conditional request enable 2 1 read-write HSMCLK_EN_0 HSMCLK disabled regardless of conditional clock requests 0 HSMCLK_EN_1 HSMCLK enabled based on any conditional clock requests 1 MCLK_EN MCLK system clock conditional request enable 1 1 read-write MCLK_EN_0 MCLK disabled regardless of conditional clock requests 0 MCLK_EN_1 MCLK enabled based on any conditional clock requests 1 MODOSC_EN Turns on the MODOSC oscillator 10 1 read-write MODOSC_EN_0 MODOSC is on only if it is used as a source for ACLK, MCLK, HSMCLK or SMCLK 0 MODOSC_EN_1 MODOSC is on 1 REFOFSEL Selects REFO nominal frequency 15 1 read-write REFOFSEL_0 32 kHz 0 REFOFSEL_1 128 kHz 1 REFO_EN Turns on the REFO oscillator 9 1 read-write REFO_EN_0 REFO is on only if it is used as a source for ACLK, MCLK, HSMCLK or SMCLK 0 REFO_EN_1 REFO is on 1 SMCLK_EN SMCLK system clock conditional request enable 3 1 read-write SMCLK_EN_0 SMCLK disabled regardless of conditional clock requests. 0 SMCLK_EN_1 SMCLK enabled based on any conditional clock requests 1 VLO_EN Turns on the VLO oscillator 8 1 read-write VLO_EN_0 VLO is on only if it is used as a source for ACLK, MCLK, HSMCLK or SMCLK. 0 VLO_EN_1 VLO is on 1 CSCLRIFG CLRIFG Clear Interrupt Flag Register 0x50 32 write-only n 0x0 0xFFFFFFFF CLR_CALIFG REFCNT period counter clear interrupt flag 15 1 write-only CLR_CALIFG_enum_write write CLR_CALIFG_0 No effect 0 CLR_CALIFG_1 Clear pending interrupt flag 1 CLR_DCOR_OPNIFG Clear DCO external resistor open circuit fault interrupt flag. 6 1 write-only CLR_DCOR_OPNIFG_enum_write write CLR_DCOR_OPNIFG_0 No effect 0 CLR_DCOR_OPNIFG_1 Clear pending interrupt flag 1 CLR_FCNTHF2IFG Start fault counter clear interrupt flag HFXT2 10 1 write-only CLR_FCNTHF2IFG_enum_write write CLR_FCNTHF2IFG_0 No effect 0 CLR_FCNTHF2IFG_1 Clear pending interrupt flag 1 CLR_FCNTHFIFG Start fault counter clear interrupt flag HFXT 9 1 write-only CLR_FCNTHFIFG_enum_write write CLR_FCNTHFIFG_0 No effect 0 CLR_FCNTHFIFG_1 Clear pending interrupt flag 1 CLR_FCNTLFIFG Start fault counter clear interrupt flag LFXT 8 1 write-only CLR_FCNTLFIFG_enum_write write CLR_FCNTLFIFG_0 No effect 0 CLR_FCNTLFIFG_1 Clear pending interrupt flag 1 CLR_HFXT2IFG Clear HFXT2 oscillator fault interrupt flag 2 1 write-only CLR_HFXT2IFG_enum_write write CLR_HFXT2IFG_0 No effect 0 CLR_HFXT2IFG_1 Clear pending interrupt flag 1 CLR_HFXTIFG Clear HFXT oscillator fault interrupt flag 1 1 write-only CLR_HFXTIFG_enum_write write CLR_HFXTIFG_0 No effect 0 CLR_HFXTIFG_1 Clear pending interrupt flag 1 CLR_LFXTIFG Clear LFXT oscillator fault interrupt flag 0 1 write-only CLR_LFXTIFG_enum_write write CLR_LFXTIFG_0 No effect 0 CLR_LFXTIFG_1 Clear pending interrupt flag 1 CLR_PLLLOSIFG PLL loss-of-signal clear interrupt flag 13 1 write-only CLR_PLLLOSIFG_enum_write write CLR_PLLLOSIFG_0 No effect 0 CLR_PLLLOSIFG_1 Clear pending interrupt flag 1 CLR_PLLOOLIFG PLL out-of-lock clear interrupt flag 12 1 write-only CLR_PLLOOLIFG_enum_write write CLR_PLLOOLIFG_0 No effect 0 CLR_PLLOOLIFG_1 Clear pending interrupt flag 1 CLR_PLLOORIFG PLL out-of-range clear interrupt flag 14 1 write-only CLR_PLLOORIFG_enum_write write CLR_PLLOORIFG_0 No effect 0 CLR_PLLOORIFG_1 Clear pending interrupt flag 1 CSCTL0 CTL0 Control 0 Register 0x4 32 read-write n 0x10000 0x0 DCOEN Enables the DCO oscillator 23 1 read-write DCOEN_0 DCO is on if it is used as a source for MCLK, HSMCLK , or SMCLK and clock is requested, otherwise it is disabled. 0 DCOEN_1 DCO is on 1 DCORES Enables the DCO external resistor mode 22 1 read-write DCORES_0 Internal resistor mode 0 DCORES_1 External resistor mode 1 DCORSEL DCO frequency range select 16 3 read-write DCORSEL_0 Nominal DCO Frequency Range (MHz): 1 to 2 0 DCORSEL_1 Nominal DCO Frequency Range (MHz): 2 to 4 1 DCORSEL_2 Nominal DCO Frequency Range (MHz): 4 to 8 2 DCORSEL_3 Nominal DCO Frequency Range (MHz): 8 to 16 3 DCORSEL_4 Nominal DCO Frequency Range (MHz): 16 to 32 4 DCORSEL_5 Nominal DCO Frequency Range (MHz): 32 to 64 5 DCOTUNE DCO frequency tuning select 0 10 read-write CSCTL1 CTL1 Control 1 Register 0x8 32 read-write n 0x33 0x0 DIVA ACLK source divider 24 3 read-write DIVA_0 f(ACLK)/1 0 DIVA_1 f(ACLK)/2 1 DIVA_2 f(ACLK)/4 2 DIVA_3 f(ACLK)/8 3 DIVA_4 f(ACLK)/16 4 DIVA_5 f(ACLK)/32 5 DIVA_6 f(ACLK)/64 6 DIVA_7 f(ACLK)/128 7 DIVHS HSMCLK source divider 20 3 read-write DIVHS_0 f(HSMCLK)/1 0 DIVHS_1 f(HSMCLK)/2 1 DIVHS_2 f(HSMCLK)/4 2 DIVHS_3 f(HSMCLK)/8 3 DIVHS_4 f(HSMCLK)/16 4 DIVHS_5 f(HSMCLK)/32 5 DIVHS_6 f(HSMCLK)/64 6 DIVHS_7 f(HSMCLK)/128 7 DIVM MCLK source divider 16 3 read-write DIVM_0 f(MCLK)/1 0 DIVM_1 f(MCLK)/2 1 DIVM_2 f(MCLK)/4 2 DIVM_3 f(MCLK)/8 3 DIVM_4 f(MCLK)/16 4 DIVM_5 f(MCLK)/32 5 DIVM_6 f(MCLK)/64 6 DIVM_7 f(MCLK)/128 7 DIVS SMCLK source divider 28 3 read-write DIVS_0 f(SMCLK)/1 0 DIVS_1 f(SMCLK)/2 1 DIVS_2 f(SMCLK)/4 2 DIVS_3 f(SMCLK)/8 3 DIVS_4 f(SMCLK)/16 4 DIVS_5 f(SMCLK)/32 5 DIVS_6 f(SMCLK)/64 6 DIVS_7 f(SMCLK)/128 7 SELA Selects the ACLK source 8 3 read-write SELA_0 when LFXT available, otherwise REFOCLK 0 SELA_1 None 1 SELA_2 None 2 SELA_3 for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities. 3 SELA_4 for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities. 4 SELA_5 for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities. 5 SELA_6 for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities. 6 SELA_7 for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities. 7 SELB Selects the BCLK source 12 1 read-write SELB_0 LFXTCLK 0 SELB_1 REFOCLK 1 SELM Selects the MCLK source 0 3 read-write SELM_0 when LFXT available, otherwise REFOCLK 0 SELM_1 None 1 SELM_2 None 2 SELM_3 None 3 SELM_4 None 4 SELM_5 when HFXT available, otherwise DCOCLK 5 SELM_6 when HFXT2 available, otherwise DCOCLK 6 SELM_7 for future use. Defaults to DCOCLK. Not recommended for use to ensure future compatibilities. 7 SELS Selects the SMCLK and HSMCLK source 4 3 read-write SELS_0 when LFXT available, otherwise REFOCLK 0 SELS_1 None 1 SELS_2 None 2 SELS_3 None 3 SELS_4 None 4 SELS_5 when HFXT available, otherwise DCOCLK 5 SELS_6 when HFXT2 available, otherwise DCOCLK 6 SELS_7 for furture use. Defaults to DCOCLK. Do not use to ensure future compatibilities. 7 CSCTL2 CTL2 Control 2 Register 0xC 32 read-write n 0x10003 0x0 HFXTBYPASS HFXT bypass select 25 1 read-write HFXTBYPASS_0 HFXT sourced by external crystal. 0 HFXTBYPASS_1 HFXT sourced by external square wave. 1 HFXTDRIVE HFXT oscillator drive selection 16 1 read-write HFXTDRIVE_0 To be used for HFXTFREQ setting 000b 0 HFXTDRIVE_1 To be used for HFXTFREQ settings 001b to 110b 1 HFXTFREQ HFXT frequency selection 20 3 read-write HFXTFREQ_0 1 MHz to 4 MHz 0 HFXTFREQ_1 >4 MHz to 8 MHz 1 HFXTFREQ_2 >8 MHz to 16 MHz 2 HFXTFREQ_3 >16 MHz to 24 MHz 3 HFXTFREQ_4 >24 MHz to 32 MHz 4 HFXTFREQ_5 >32 MHz to 40 MHz 5 HFXTFREQ_6 >40 MHz to 48 MHz 6 HFXT_EN Turns on the HFXT oscillator regardless if used as a clock resource 24 1 read-write HFXT_EN_0 HFXT is on if it is used as a source for MCLK, HSMCLK , or SMCLK and is selected via the port selection and not in bypass mode of operation. 0 HFXT_EN_1 HFXT is on if HFXT is selected via the port selection and HFXT is not in bypass mode of operation. 1 LFXTAGCOFF Disables the automatic gain control of the LFXT crystal 7 1 read-write LFXTAGCOFF_0 AGC enabled. 0 LFXTAGCOFF_1 AGC disabled. 1 LFXTBYPASS LFXT bypass select 9 1 read-write LFXTBYPASS_0 LFXT sourced by external crystal. 0 LFXTBYPASS_1 LFXT sourced by external square wave. 1 LFXTDRIVE LFXT oscillator current can be adjusted to its drive needs 0 2 read-write LFXTDRIVE_0 Lowest drive strength and current consumption LFXT oscillator. 0 LFXTDRIVE_1 Increased drive strength LFXT oscillator. 1 LFXTDRIVE_2 Increased drive strength LFXT oscillator. 2 LFXTDRIVE_3 Maximum drive strength and maximum current consumption LFXT oscillator. 3 LFXT_EN Turns on the LFXT oscillator regardless if used as a clock resource 8 1 read-write LFXT_EN_0 LFXT is on if it is used as a source for ACLK, MCLK, HSMCLK , or SMCLK and is selected via the port selection and not in bypass mode of operation. 0 LFXT_EN_1 LFXT is on if LFXT is selected via the port selection and LFXT is not in bypass mode of operation. 1 CSCTL3 CTL3 Control 3 Register 0x10 32 read-write n 0xBBB 0xFFFFFFFF FCNTHF Start flag counter for HFXT 4 2 read-write FCNTHF_0 2048 cycles 0 FCNTHF_1 4096 cycles 1 FCNTHF_2 8192 cycles 2 FCNTHF_3 16384 cycles 3 FCNTHF2 Start flag counter for HFXT2 8 2 read-write FCNTHF2_0 2048 cycles 0 FCNTHF2_1 4096 cycles 1 FCNTHF2_2 8192 cycles 2 FCNTHF2_3 16384 cycles 3 FCNTHF2_EN Enable start fault counter for HFXT2 11 1 read-write FCNTHF2_EN_0 Startup fault counter disabled. Counter is cleared. 0 FCNTHF2_EN_1 Startup fault counter enabled. 1 FCNTHF_EN Enable start fault counter for HFXT 7 1 read-write FCNTHF_EN_0 Startup fault counter disabled. Counter is cleared. 0 FCNTHF_EN_1 Startup fault counter enabled. 1 FCNTLF Start flag counter for LFXT 0 2 read-write FCNTLF_0 4096 cycles 0 FCNTLF_1 8192 cycles 1 FCNTLF_2 16384 cycles 2 FCNTLF_3 32768 cycles 3 FCNTLF_EN Enable start fault counter for LFXT 3 1 read-write FCNTLF_EN_0 Startup fault counter disabled. Counter is cleared. 0 FCNTLF_EN_1 Startup fault counter enabled. 1 RFCNTHF Reset start fault counter for HFXT 6 1 write-only RFCNTHF_enum_write write RFCNTHF_0 Not applicable. Always reads as zero due to self clearing. 0 RFCNTHF_1 Restarts the counter immediately. 1 RFCNTHF2 Reset start fault counter for HFXT2 10 1 write-only RFCNTHF2_enum_write write RFCNTHF2_0 Not applicable. Always reads as zero due to self clearing. 0 RFCNTHF2_1 Restarts the counter immediately. 1 RFCNTLF Reset start fault counter for LFXT 2 1 write-only RFCNTLF_enum_write write RFCNTLF_0 Not applicable. Always reads as zero due to self clearing. 0 RFCNTLF_1 Restarts the counter immediately. 1 CSDCOERCAL0 DCOERCAL0 DCO External Resistor Cailbration 0 Register 0x60 32 read-write n 0x1000000 0x0 DCO_FCAL_RSEL04 DCO frequency calibration for DCO frequency range (DCORSEL) 0 to 4. 16 10 read-write DCO_TCCAL DCO Temperature compensation calibration 0 2 read-write CSDCOERCAL1 DCOERCAL1 DCO External Resistor Calibration 1 Register 0x64 32 read-write n 0x100 0xFFFFFFFF DCO_FCAL_RSEL5 DCO frequency calibration for DCO frequency range (DCORSEL) 5. 0 10 read-write CSIE IE Interrupt Enable Register 0x40 32 read-write n 0x0 0xFFFFFFFF CALIE REFCNT period counter interrupt enable 15 1 read-write CALIE_0 Interrupt disabled 0 CALIE_1 Interrupt enabled 1 DCOR_OPNIE DCO external resistor open circuit fault flag interrupt enable. 6 1 read-write DCOR_OPNIE_0 Interrupt disabled 0 DCOR_OPNIE_1 Interrupt enabled 1 FCNTHF2IE Start fault counter interrupt enable HFXT2 10 1 read-write FCNTHF2IE_0 Interrupt disabled 0 FCNTHF2IE_1 Interrupt enabled 1 FCNTHFIE Start fault counter interrupt enable HFXT 9 1 read-write FCNTHFIE_0 Interrupt disabled 0 FCNTHFIE_1 Interrupt enabled 1 FCNTLFIE Start fault counter interrupt enable LFXT 8 1 read-write FCNTLFIE_0 Interrupt disabled 0 FCNTLFIE_1 Interrupt enabled 1 HFXT2IE HFXT2 oscillator fault flag interrupt enable 2 1 read-write HFXT2IE_0 Interrupt disabled 0 HFXT2IE_1 Interrupt enabled 1 HFXTIE HFXT oscillator fault flag interrupt enable 1 1 read-write HFXTIE_0 Interrupt disabled 0 HFXTIE_1 Interrupt enabled 1 LFXTIE LFXT oscillator fault flag interrupt enable 0 1 read-write LFXTIE_0 Interrupt disabled 0 LFXTIE_1 Interrupt enabled 1 PLLLOSIE PLL loss-of-signal interrupt enable 13 1 read-write PLLLOSIE_0 Interrupt disabled 0 PLLLOSIE_1 Interrupt enabled 1 PLLOOLIE PLL out-of-lock interrupt enable 12 1 read-write PLLOOLIE_0 Interrupt disabled 0 PLLOOLIE_1 Interrupt enabled 1 PLLOORIE PLL out-of-range interrupt enable 14 1 read-write PLLOORIE_0 Interrupt disabled 0 PLLOORIE_1 Interrupt enabled 1 CSIFG IFG Interrupt Flag Register 0x48 32 read-only n 0x1 0xFFFFFFFF CALIFG REFCNT period counter expired 15 1 read-only CALIFG_enum_read read CALIFG_0 REFCNT period counter not expired 0 CALIFG_1 REFCNT period counter expired 1 DCOR_OPNIFG DCO external resistor open circuit fault flag. 6 1 read-only DCOR_OPNIFG_enum_read read DCOR_OPNIFG_0 DCO external resistor present 0 DCOR_OPNIFG_1 DCO external resistor open circuit fault 1 DCOR_SHTIFG DCO external resistor short circuit fault flag. 5 1 read-only DCOR_SHTIFG_enum_read read DCOR_SHTIFG_0 DCO external resistor present 0 DCOR_SHTIFG_1 DCO external resistor short circuit fault 1 FCNTHF2IFG Start fault counter interrupt flag HFXT2 11 1 read-only FCNTHF2IFG_enum_read read FCNTHF2IFG_0 Start counter not expired 0 FCNTHF2IFG_1 Start counter expired 1 FCNTHFIFG Start fault counter interrupt flag HFXT 9 1 read-only FCNTHFIFG_enum_read read FCNTHFIFG_0 Start counter not expired 0 FCNTHFIFG_1 Start counter expired 1 FCNTLFIFG Start fault counter interrupt flag LFXT 8 1 read-only FCNTLFIFG_enum_read read FCNTLFIFG_0 Start counter not expired 0 FCNTLFIFG_1 Start counter expired 1 HFXT2IFG HFXT2 oscillator fault flag 2 1 read-only HFXT2IFG_enum_read read HFXT2IFG_0 No fault condition occurred after the last reset 0 HFXT2IFG_1 HFXT2 fault. A HFXT2 fault occurred after the last reset 1 HFXTIFG HFXT oscillator fault flag 1 1 read-only HFXTIFG_enum_read read HFXTIFG_0 No fault condition occurred after the last reset 0 HFXTIFG_1 HFXT fault. A HFXT fault occurred after the last reset 1 LFXTIFG LFXT oscillator fault flag 0 1 read-only LFXTIFG_enum_read read LFXTIFG_0 No fault condition occurred after the last reset 0 LFXTIFG_1 LFXT fault. A LFXT fault occurred after the last reset 1 PLLLOSIFG PLL loss-of-signal interrupt flag 13 1 read-only PLLLOSIFG_enum_read read PLLLOSIFG_0 No interrupt pending 0 PLLLOSIFG_1 Interrupt pending 1 PLLOOLIFG PLL out-of-lock interrupt flag 12 1 read-only PLLOOLIFG_enum_read read PLLOOLIFG_0 No interrupt pending 0 PLLOOLIFG_1 Interrupt pending 1 PLLOORIFG PLL out-of-range interrupt flag 14 1 read-only PLLOORIFG_enum_read read PLLOORIFG_0 No interrupt pending 0 PLLOORIFG_1 Interrupt pending 1 CSKEY KEY Key Register 0x0 32 read-write n 0xA596 0x0 CSKEY Write xxxx_695Ah to unlock 0 16 read-write CSSETIFG SETIFG Set Interrupt Flag Register 0x58 32 write-only n 0x0 0xFFFFFFFF SET_CALIFG REFCNT period counter set interrupt flag 15 1 write-only SET_CALIFG_enum_write write SET_CALIFG_0 No effect 0 SET_CALIFG_1 Set pending interrupt flag 1 SET_DCOR_OPNIFG Set DCO external resistor open circuit fault interrupt flag. 6 1 write-only SET_DCOR_OPNIFG_enum_write write SET_DCOR_OPNIFG_0 No effect 0 SET_DCOR_OPNIFG_1 Set pending interrupt flag 1 SET_FCNTHF2IFG Start fault counter set interrupt flag HFXT2 10 1 write-only SET_FCNTHF2IFG_enum_write write SET_FCNTHF2IFG_0 No effect 0 SET_FCNTHF2IFG_1 Set pending interrupt flag 1 SET_FCNTHFIFG Start fault counter set interrupt flag HFXT 9 1 write-only SET_FCNTHFIFG_enum_write write SET_FCNTHFIFG_0 No effect 0 SET_FCNTHFIFG_1 Set pending interrupt flag 1 SET_FCNTLFIFG Start fault counter set interrupt flag LFXT 8 1 write-only SET_FCNTLFIFG_enum_write write SET_FCNTLFIFG_0 No effect 0 SET_FCNTLFIFG_1 Set pending interrupt flag 1 SET_HFXT2IFG Set HFXT2 oscillator fault interrupt flag 2 1 write-only SET_HFXT2IFG_enum_write write SET_HFXT2IFG_0 No effect 0 SET_HFXT2IFG_1 Set pending interrupt flag 1 SET_HFXTIFG Set HFXT oscillator fault interrupt flag 1 1 write-only SET_HFXTIFG_enum_write write SET_HFXTIFG_0 No effect 0 SET_HFXTIFG_1 Set pending interrupt flag 1 SET_LFXTIFG Set LFXT oscillator fault interrupt flag 0 1 write-only SET_LFXTIFG_enum_write write SET_LFXTIFG_0 No effect 0 SET_LFXTIFG_1 Set pending interrupt flag 1 SET_PLLLOSIFG PLL loss-of-signal set interrupt flag 13 1 write-only SET_PLLLOSIFG_enum_write write SET_PLLLOSIFG_0 No effect 0 SET_PLLLOSIFG_1 Set pending interrupt flag 1 SET_PLLOOLIFG PLL out-of-lock set interrupt flag 12 1 write-only SET_PLLOOLIFG_enum_write write SET_PLLOOLIFG_0 No effect 0 SET_PLLOOLIFG_1 Set pending interrupt flag 1 SET_PLLOORIFG PLL out-of-range set interrupt flag 14 1 write-only SET_PLLOORIFG_enum_write write SET_PLLOORIFG_0 No effect 0 SET_PLLOORIFG_1 Set pending interrupt flag 1 CSSTAT STAT Status Register 0x34 32 read-only n 0x3 0xFFFF01FF ACLK_ON ACLK system clock status 16 1 read-only ACLK_ON_enum_read read ACLK_ON_0 Inactive 0 ACLK_ON_1 Active 1 ACLK_READY ACLK Ready status 24 1 read-only ACLK_READY_enum_read read ACLK_READY_0 Not ready 0 ACLK_READY_1 Ready 1 BCLK_READY BCLK Ready status 28 1 read-only BCLK_READY_enum_read read BCLK_READY_0 Not ready 0 BCLK_READY_1 Ready 1 DCOBIAS_ON DCO bias status 1 1 read-only DCOBIAS_ON_enum_read read DCOBIAS_ON_0 Inactive 0 DCOBIAS_ON_1 Active 1 DCO_ON DCO status 0 1 read-only DCO_ON_enum_read read DCO_ON_0 Inactive 0 DCO_ON_1 Active 1 HFXT2_ON HFXT2 status 3 1 read-only HFXT2_ON_enum_read read HFXT2_ON_0 Inactive 0 HFXT2_ON_1 Active 1 HFXT_ON HFXT status 2 1 read-only HFXT_ON_enum_read read HFXT_ON_0 Inactive 0 HFXT_ON_1 Active 1 HSMCLK_ON HSMCLK system clock status 18 1 read-only HSMCLK_ON_enum_read read HSMCLK_ON_0 Inactive 0 HSMCLK_ON_1 Active 1 HSMCLK_READY HSMCLK Ready status 26 1 read-only HSMCLK_READY_enum_read read HSMCLK_READY_0 Not ready 0 HSMCLK_READY_1 Ready 1 LFXTCLK_ON LFXTCLK system clock status 22 1 read-only LFXTCLK_ON_enum_read read LFXTCLK_ON_0 Inactive 0 LFXTCLK_ON_1 Active 1 LFXT_ON LFXT status 6 1 read-only LFXT_ON_enum_read read LFXT_ON_0 Inactive 0 LFXT_ON_1 Active 1 MCLK_ON MCLK system clock status 17 1 read-only MCLK_ON_enum_read read MCLK_ON_0 Inactive 0 MCLK_ON_1 Active 1 MCLK_READY MCLK Ready status 25 1 read-only MCLK_READY_enum_read read MCLK_READY_0 Not ready 0 MCLK_READY_1 Ready 1 MODCLK_ON MODCLK system clock status 20 1 read-only MODCLK_ON_enum_read read MODCLK_ON_0 Inactive 0 MODCLK_ON_1 Active 1 MODOSC_ON MODOSC status 4 1 read-only MODOSC_ON_enum_read read MODOSC_ON_0 Inactive 0 MODOSC_ON_1 Active 1 REFOCLK_ON REFOCLK system clock status 23 1 read-only REFOCLK_ON_enum_read read REFOCLK_ON_0 Inactive 0 REFOCLK_ON_1 Active 1 REFO_ON REFO status 7 1 read-only REFO_ON_enum_read read REFO_ON_0 Inactive 0 REFO_ON_1 Active 1 SMCLK_ON SMCLK system clock status 19 1 read-only SMCLK_ON_enum_read read SMCLK_ON_0 Inactive 0 SMCLK_ON_1 Active 1 SMCLK_READY SMCLK Ready status 27 1 read-only SMCLK_READY_enum_read read SMCLK_READY_0 Not ready 0 SMCLK_READY_1 Ready 1 VLOCLK_ON VLOCLK system clock status 21 1 read-only VLOCLK_ON_enum_read read VLOCLK_ON_0 Inactive 0 VLOCLK_ON_1 Active 1 VLO_ON VLO status 5 1 read-only VLO_ON_enum_read read VLO_ON_0 Inactive 0 VLO_ON_1 Active 1 DIO DIO DIO 0x40004C00 0x0 0x138 registers n PORT1_IRQ Port1 Interrupt 35 PORT2_IRQ Port2 Interrupt 36 PORT3_IRQ Port3 Interrupt 37 PORT4_IRQ Port4 Interrupt 38 PORT5_IRQ Port5 Interrupt 39 PORT6_IRQ Port6 Interrupt 40 P10IV P10IV Port 10 Interrupt Vector Register 0x9E 16 read-only n 0x0 0x0 P10IV Port 10 interrupt vector value 0 5 read-only P10IV_enum_read read P10IV_0 No interrupt pending 0 P10IV_10 Interrupt Source: Port 10.4 interrupt Interrupt Flag: P10IFG4 10 P10IV_12 Interrupt Source: Port 10.5 interrupt Interrupt Flag: P10IFG5 12 P10IV_14 Interrupt Source: Port 10.6 interrupt Interrupt Flag: P10IFG6 14 P10IV_16 Interrupt Source: Port 10.7 interrupt Interrupt Flag: P10IFG7 Interrupt Priority: Lowest 16 P10IV_2 Interrupt Source: Port 10.0 interrupt Interrupt Flag: P10IFG0 Interrupt Priority: Highest 2 P10IV_4 Interrupt Source: Port 10.1 interrupt Interrupt Flag: P10IFG1 4 P10IV_6 Interrupt Source: Port 10.2 interrupt Interrupt Flag: P10IFG2 6 P10IV_8 Interrupt Source: Port 10.3 interrupt Interrupt Flag: P10IFG3 8 P1IV P1IV Port 1 Interrupt Vector Register 0xE 16 read-only n 0x0 0xFFFF P1IV Port 1 interrupt vector value 0 5 read-only P1IV_enum_read read P1IV_0 No interrupt pending 0 P1IV_10 Interrupt Source: Port 1.4 interrupt Interrupt Flag: P1IFG4 10 P1IV_12 Interrupt Source: Port 1.5 interrupt Interrupt Flag: P1IFG5 12 P1IV_14 Interrupt Source: Port 1.6 interrupt Interrupt Flag: P1IFG6 14 P1IV_16 Interrupt Source: Port 1.7 interrupt Interrupt Flag: P1IFG7 Interrupt Priority: Lowest 16 P1IV_2 Interrupt Source: Port 1.0 interrupt Interrupt Flag: P1IFG0 Interrupt Priority: Highest 2 P1IV_4 Interrupt Source: Port 1.1 interrupt Interrupt Flag: P1IFG1 4 P1IV_6 Interrupt Source: Port 1.2 interrupt Interrupt Flag: P1IFG2 6 P1IV_8 Interrupt Source: Port 1.3 interrupt Interrupt Flag: P1IFG3 8 P2IV P2IV Port 2 Interrupt Vector Register 0x1E 16 read-only n 0x0 0x0 P2IV Port 2 interrupt vector value 0 5 read-only P2IV_enum_read read P2IV_0 No interrupt pending 0 P2IV_10 Interrupt Source: Port 2.4 interrupt Interrupt Flag: P2IFG4 10 P2IV_12 Interrupt Source: Port 2.5 interrupt Interrupt Flag: P2IFG5 12 P2IV_14 Interrupt Source: Port 2.6 interrupt Interrupt Flag: P2IFG6 14 P2IV_16 Interrupt Source: Port 2.7 interrupt Interrupt Flag: P2IFG7 Interrupt Priority: Lowest 16 P2IV_2 Interrupt Source: Port 2.0 interrupt Interrupt Flag: P2IFG0 Interrupt Priority: Highest 2 P2IV_4 Interrupt Source: Port 2.1 interrupt Interrupt Flag: P2IFG1 4 P2IV_6 Interrupt Source: Port 2.2 interrupt Interrupt Flag: P2IFG2 6 P2IV_8 Interrupt Source: Port 2.3 interrupt Interrupt Flag: P2IFG3 8 P3IV P3IV Port 3 Interrupt Vector Register 0x2E 16 read-only n 0x0 0xFFFF P3IV Port 3 interrupt vector value 0 5 read-only P3IV_enum_read read P3IV_0 No interrupt pending 0 P3IV_10 Interrupt Source: Port 3.4 interrupt Interrupt Flag: P3IFG4 10 P3IV_12 Interrupt Source: Port 3.5 interrupt Interrupt Flag: P3IFG5 12 P3IV_14 Interrupt Source: Port 3.6 interrupt Interrupt Flag: P3IFG6 14 P3IV_16 Interrupt Source: Port 3.7 interrupt Interrupt Flag: P3IFG7 Interrupt Priority: Lowest 16 P3IV_2 Interrupt Source: Port 3.0 interrupt Interrupt Flag: P3IFG0 Interrupt Priority: Highest 2 P3IV_4 Interrupt Source: Port 3.1 interrupt Interrupt Flag: P3IFG1 4 P3IV_6 Interrupt Source: Port 3.2 interrupt Interrupt Flag: P3IFG2 6 P3IV_8 Interrupt Source: Port 3.3 interrupt Interrupt Flag: P3IFG3 8 P4IV P4IV Port 4 Interrupt Vector Register 0x3E 16 read-only n 0x0 0x0 P4IV Port 4 interrupt vector value 0 5 read-only P4IV_enum_read read P4IV_0 No interrupt pending 0 P4IV_10 Interrupt Source: Port 4.4 interrupt Interrupt Flag: P4IFG4 10 P4IV_12 Interrupt Source: Port 4.5 interrupt Interrupt Flag: P4IFG5 12 P4IV_14 Interrupt Source: Port 4.6 interrupt Interrupt Flag: P4IFG6 14 P4IV_16 Interrupt Source: Port 4.7 interrupt Interrupt Flag: P4IFG7 Interrupt Priority: Lowest 16 P4IV_2 Interrupt Source: Port 4.0 interrupt Interrupt Flag: P4IFG0 Interrupt Priority: Highest 2 P4IV_4 Interrupt Source: Port 4.1 interrupt Interrupt Flag: P4IFG1 4 P4IV_6 Interrupt Source: Port 4.2 interrupt Interrupt Flag: P4IFG2 6 P4IV_8 Interrupt Source: Port 4.3 interrupt Interrupt Flag: P4IFG3 8 P5IV P5IV Port 5 Interrupt Vector Register 0x4E 16 read-only n 0x0 0xFFFF P5IV Port 5 interrupt vector value 0 5 read-only P5IV_enum_read read P5IV_0 No interrupt pending 0 P5IV_10 Interrupt Source: Port 5.4 interrupt Interrupt Flag: P5IFG4 10 P5IV_12 Interrupt Source: Port 5.5 interrupt Interrupt Flag: P5IFG5 12 P5IV_14 Interrupt Source: Port 5.6 interrupt Interrupt Flag: P5IFG6 14 P5IV_16 Interrupt Source: Port 5.7 interrupt Interrupt Flag: P5IFG7 Interrupt Priority: Lowest 16 P5IV_2 Interrupt Source: Port 5.0 interrupt Interrupt Flag: P5IFG0 Interrupt Priority: Highest 2 P5IV_4 Interrupt Source: Port 5.1 interrupt Interrupt Flag: P5IFG1 4 P5IV_6 Interrupt Source: Port 5.2 interrupt Interrupt Flag: P5IFG2 6 P5IV_8 Interrupt Source: Port 5.3 interrupt Interrupt Flag: P5IFG3 8 P6IV P6IV Port 6 Interrupt Vector Register 0x5E 16 read-only n 0x0 0x0 P6IV Port 6 interrupt vector value 0 5 read-only P6IV_enum_read read P6IV_0 No interrupt pending 0 P6IV_10 Interrupt Source: Port 6.4 interrupt Interrupt Flag: P6IFG4 10 P6IV_12 Interrupt Source: Port 6.5 interrupt Interrupt Flag: P6IFG5 12 P6IV_14 Interrupt Source: Port 6.6 interrupt Interrupt Flag: P6IFG6 14 P6IV_16 Interrupt Source: Port 6.7 interrupt Interrupt Flag: P6IFG7 Interrupt Priority: Lowest 16 P6IV_2 Interrupt Source: Port 6.0 interrupt Interrupt Flag: P6IFG0 Interrupt Priority: Highest 2 P6IV_4 Interrupt Source: Port 6.1 interrupt Interrupt Flag: P6IFG1 4 P6IV_6 Interrupt Source: Port 6.2 interrupt Interrupt Flag: P6IFG2 6 P6IV_8 Interrupt Source: Port 6.3 interrupt Interrupt Flag: P6IFG3 8 P7IV P7IV Port 7 Interrupt Vector Register 0x6E 16 read-only n 0x0 0xFFFF P7IV Port 7 interrupt vector value 0 5 read-only P7IV_enum_read read P7IV_0 No interrupt pending 0 P7IV_10 Interrupt Source: Port 7.4 interrupt Interrupt Flag: P7IFG4 10 P7IV_12 Interrupt Source: Port 7.5 interrupt Interrupt Flag: P7IFG5 12 P7IV_14 Interrupt Source: Port 7.6 interrupt Interrupt Flag: P7IFG6 14 P7IV_16 Interrupt Source: Port 7.7 interrupt Interrupt Flag: P7IFG7 Interrupt Priority: Lowest 16 P7IV_2 Interrupt Source: Port 7.0 interrupt Interrupt Flag: P7IFG0 Interrupt Priority: Highest 2 P7IV_4 Interrupt Source: Port 7.1 interrupt Interrupt Flag: P7IFG1 4 P7IV_6 Interrupt Source: Port 7.2 interrupt Interrupt Flag: P7IFG2 6 P7IV_8 Interrupt Source: Port 7.3 interrupt Interrupt Flag: P7IFG3 8 P8IV P8IV Port 8 Interrupt Vector Register 0x7E 16 read-only n 0x0 0x0 P8IV Port 8 interrupt vector value 0 5 read-only P8IV_enum_read read P8IV_0 No interrupt pending 0 P8IV_10 Interrupt Source: Port 8.4 interrupt Interrupt Flag: P8IFG4 10 P8IV_12 Interrupt Source: Port 8.5 interrupt Interrupt Flag: P8IFG5 12 P8IV_14 Interrupt Source: Port 8.6 interrupt Interrupt Flag: P8IFG6 14 P8IV_16 Interrupt Source: Port 8.7 interrupt Interrupt Flag: P8IFG7 Interrupt Priority: Lowest 16 P8IV_2 Interrupt Source: Port 8.0 interrupt Interrupt Flag: P8IFG0 Interrupt Priority: Highest 2 P8IV_4 Interrupt Source: Port 8.1 interrupt Interrupt Flag: P8IFG1 4 P8IV_6 Interrupt Source: Port 8.2 interrupt Interrupt Flag: P8IFG2 6 P8IV_8 Interrupt Source: Port 8.3 interrupt Interrupt Flag: P8IFG3 8 P9IV P9IV Port 9 Interrupt Vector Register 0x8E 16 read-only n 0x0 0xFFFF P9IV Port 9 interrupt vector value 0 5 read-only P9IV_enum_read read P9IV_0 No interrupt pending 0 P9IV_10 Interrupt Source: Port 9.4 interrupt Interrupt Flag: P9IFG4 10 P9IV_12 Interrupt Source: Port 9.5 interrupt Interrupt Flag: P9IFG5 12 P9IV_14 Interrupt Source: Port 9.6 interrupt Interrupt Flag: P9IFG6 14 P9IV_16 Interrupt Source: Port 9.7 interrupt Interrupt Flag: P9IFG7 Interrupt Priority: Lowest 16 P9IV_2 Interrupt Source: Port 9.0 interrupt Interrupt Flag: P9IFG0 Interrupt Priority: Highest 2 P9IV_4 Interrupt Source: Port 9.1 interrupt Interrupt Flag: P9IFG1 4 P9IV_6 Interrupt Source: Port 9.2 interrupt Interrupt Flag: P9IFG2 6 P9IV_8 Interrupt Source: Port 9.3 interrupt Interrupt Flag: P9IFG3 8 PADIR PADIR Port A Direction 0x4 16 read-write n 0x0 0xFFFF P1DIR Port 1 Direction 0 8 read-write P2DIR Port 2 Direction 8 8 read-write PADS PADS Port A Drive Strength 0x8 16 read-write n 0x0 0x0 P1DS Port 1 Drive Strength 0 8 read-write P2DS Port 2 Drive Strength 8 8 read-write PAIE PAIE Port A Interrupt Enable 0x1A 16 read-write n 0x0 0xFFFF P1IE Port 1 Interrupt Enable 0 8 read-write P2IE Port 2 Interrupt Enable 8 8 read-write PAIES PAIES Port A Interrupt Edge Select 0x18 16 read-write n 0x0 0x0 P1IES Port 1 Interrupt Edge Select 0 8 read-write P2IES Port 2 Interrupt Edge Select 8 8 read-write PAIFG PAIFG Port A Interrupt Flag 0x1C 16 read-write n 0x0 0xFFFF P1IFG Port 1 Interrupt Flag 0 8 read-write P2IFG Port 2 Interrupt Flag 8 8 read-write PAIN PAIN Port A Input 0x0 16 read-only n 0x0 0x0 P1IN Port 1 Input 0 8 read-only P2IN Port 2 Input 8 8 read-only PAOUT PAOUT Port A Output 0x2 16 read-write n 0x0 0x0 P1OUT Port 1 Output 0 8 read-write P2OUT Port 2 Output 8 8 read-write PAREN PAREN Port A Resistor Enable 0x6 16 read-write n 0x0 0xFFFF P1REN Port 1 Resistor Enable 0 8 read-write P2REN Port 2 Resistor Enable 8 8 read-write PASEL0 PASEL0 Port A Select 0 0xA 16 read-write n 0x0 0xFFFF P1SEL0 Port 1 Select 0 0 8 read-write P2SEL0 Port 2 Select 0 8 8 read-write PASEL1 PASEL1 Port A Select 1 0xC 16 read-write n 0x0 0xFFFF P1SEL1 Port 1 Select 1 0 8 read-write P2SEL1 Port 2 Select 1 8 8 read-write PASELC PASELC Port A Complement Select 0x16 16 read-write n 0x0 0xFFFF P1SELC Port 1 Complement Select 0 8 read-write P2SELC Port 2 Complement Select 8 8 read-write PBDIR PBDIR Port B Direction 0x24 16 read-write n 0x0 0xFFFF P3DIR Port 3 Direction 0 8 read-write P4DIR Port 4 Direction 8 8 read-write PBDS PBDS Port B Drive Strength 0x28 16 read-write n 0x0 0x0 P3DS Port 3 Drive Strength 0 8 read-write P4DS Port 4 Drive Strength 8 8 read-write PBIE PBIE Port B Interrupt Enable 0x3A 16 read-write n 0x0 0xFFFF P3IE Port 3 Interrupt Enable 0 8 read-write P4IE Port 4 Interrupt Enable 8 8 read-write PBIES PBIES Port B Interrupt Edge Select 0x38 16 read-write n 0x0 0x0 P3IES Port 3 Interrupt Edge Select 0 8 read-write P4IES Port 4 Interrupt Edge Select 8 8 read-write PBIFG PBIFG Port B Interrupt Flag 0x3C 16 read-write n 0x0 0xFFFF P3IFG Port 3 Interrupt Flag 0 8 read-write P4IFG Port 4 Interrupt Flag 8 8 read-write PBIN PBIN Port B Input 0x20 16 read-only n 0x0 0x0 P3IN Port 3 Input 0 8 read-only P4IN Port 4 Input 8 8 read-only PBOUT PBOUT Port B Output 0x22 16 read-write n 0x0 0x0 P3OUT Port 3 Output 0 8 read-write P4OUT Port 4 Output 8 8 read-write PBREN PBREN Port B Resistor Enable 0x26 16 read-write n 0x0 0xFFFF P3REN Port 3 Resistor Enable 0 8 read-write P4REN Port 4 Resistor Enable 8 8 read-write PBSEL0 PBSEL0 Port B Select 0 0x2A 16 read-write n 0x0 0xFFFF P3SEL0 Port 3 Select 0 0 8 read-write P4SEL0 Port 4 Select 0 8 8 read-write PBSEL1 PBSEL1 Port B Select 1 0x2C 16 read-write n 0x0 0xFFFF P3SEL1 Port 3 Select 1 0 8 read-write P4SEL1 Port 4 Select 1 8 8 read-write PBSELC PBSELC Port B Complement Select 0x36 16 read-write n 0x0 0xFFFF P3SELC Port 3 Complement Select 0 8 read-write P4SELC Port 4 Complement Select 8 8 read-write PCDIR PCDIR Port C Direction 0x44 16 read-write n 0x0 0xFFFF P5DIR Port 5 Direction 0 8 read-write P6DIR Port 6 Direction 8 8 read-write PCDS PCDS Port C Drive Strength 0x48 16 read-write n 0x0 0x0 P5DS Port 5 Drive Strength 0 8 read-write P6DS Port 6 Drive Strength 8 8 read-write PCIE PCIE Port C Interrupt Enable 0x5A 16 read-write n 0x0 0xFFFF P5IE Port 5 Interrupt Enable 0 8 read-write P6IE Port 6 Interrupt Enable 8 8 read-write PCIES PCIES Port C Interrupt Edge Select 0x58 16 read-write n 0x0 0x0 P5IES Port 5 Interrupt Edge Select 0 8 read-write P6IES Port 6 Interrupt Edge Select 8 8 read-write PCIFG PCIFG Port C Interrupt Flag 0x5C 16 read-write n 0x0 0xFFFF P5IFG Port 5 Interrupt Flag 0 8 read-write P6IFG Port 6 Interrupt Flag 8 8 read-write PCIN PCIN Port C Input 0x40 16 read-only n 0x0 0x0 P5IN Port 5 Input 0 8 read-only P6IN Port 6 Input 8 8 read-only PCOUT PCOUT Port C Output 0x42 16 read-write n 0x0 0x0 P5OUT Port 5 Output 0 8 read-write P6OUT Port 6 Output 8 8 read-write PCREN PCREN Port C Resistor Enable 0x46 16 read-write n 0x0 0xFFFF P5REN Port 5 Resistor Enable 0 8 read-write P6REN Port 6 Resistor Enable 8 8 read-write PCSEL0 PCSEL0 Port C Select 0 0x4A 16 read-write n 0x0 0xFFFF P5SEL0 Port 5 Select 0 0 8 read-write P6SEL0 Port 6 Select 0 8 8 read-write PCSEL1 PCSEL1 Port C Select 1 0x4C 16 read-write n 0x0 0xFFFF P5SEL1 Port 5 Select 1 0 8 read-write P6SEL1 Port 6 Select 1 8 8 read-write PCSELC PCSELC Port C Complement Select 0x56 16 read-write n 0x0 0xFFFF P5SELC Port 5 Complement Select 0 8 read-write P6SELC Port 6 Complement Select 8 8 read-write PDDIR PDDIR Port D Direction 0x64 16 read-write n 0x0 0xFFFF P7DIR Port 7 Direction 0 8 read-write P8DIR Port 8 Direction 8 8 read-write PDDS PDDS Port D Drive Strength 0x68 16 read-write n 0x0 0x0 P7DS Port 7 Drive Strength 0 8 read-write P8DS Port 8 Drive Strength 8 8 read-write PDIE PDIE Port D Interrupt Enable 0x7A 16 read-write n 0x0 0xFFFF P7IE Port 7 Interrupt Enable 0 8 read-write P8IE Port 8 Interrupt Enable 8 8 read-write PDIES PDIES Port D Interrupt Edge Select 0x78 16 read-write n 0x0 0x0 P7IES Port 7 Interrupt Edge Select 0 8 read-write P8IES Port 8 Interrupt Edge Select 8 8 read-write PDIFG PDIFG Port D Interrupt Flag 0x7C 16 read-write n 0x0 0xFFFF P7IFG Port 7 Interrupt Flag 0 8 read-write P8IFG Port 8 Interrupt Flag 8 8 read-write PDIN PDIN Port D Input 0x60 16 read-only n 0x0 0x0 P7IN Port 7 Input 0 8 read-only P8IN Port 8 Input 8 8 read-only PDOUT PDOUT Port D Output 0x62 16 read-write n 0x0 0x0 P7OUT Port 7 Output 0 8 read-write P8OUT Port 8 Output 8 8 read-write PDREN PDREN Port D Resistor Enable 0x66 16 read-write n 0x0 0xFFFF P7REN Port 7 Resistor Enable 0 8 read-write P8REN Port 8 Resistor Enable 8 8 read-write PDSEL0 PDSEL0 Port D Select 0 0x6A 16 read-write n 0x0 0xFFFF P7SEL0 Port 7 Select 0 0 8 read-write P8SEL0 Port 8 Select 0 8 8 read-write PDSEL1 PDSEL1 Port D Select 1 0x6C 16 read-write n 0x0 0xFFFF P7SEL1 Port 7 Select 1 0 8 read-write P8SEL1 Port 8 Select 1 8 8 read-write PDSELC PDSELC Port D Complement Select 0x76 16 read-write n 0x0 0xFFFF P7SELC Port 7 Complement Select 0 8 read-write P8SELC Port 8 Complement Select 8 8 read-write PEDIR PEDIR Port E Direction 0x84 16 read-write n 0x0 0xFFFF P10DIR Port 10 Direction 8 8 read-write P9DIR Port 9 Direction 0 8 read-write PEDS PEDS Port E Drive Strength 0x88 16 read-write n 0x0 0x0 P10DS Port 10 Drive Strength 8 8 read-write P9DS Port 9 Drive Strength 0 8 read-write PEIE PEIE Port E Interrupt Enable 0x9A 16 read-write n 0x0 0xFFFF P10IE Port 10 Interrupt Enable 8 8 read-write P9IE Port 9 Interrupt Enable 0 8 read-write PEIES PEIES Port E Interrupt Edge Select 0x98 16 read-write n 0x0 0x0 P10IES Port 10 Interrupt Edge Select 8 8 read-write P9IES Port 9 Interrupt Edge Select 0 8 read-write PEIFG PEIFG Port E Interrupt Flag 0x9C 16 read-write n 0x0 0xFFFF P10IFG Port 10 Interrupt Flag 8 8 read-write P9IFG Port 9 Interrupt Flag 0 8 read-write PEIN PEIN Port E Input 0x80 16 read-only n 0x0 0x0 P10IN Port 10 Input 8 8 read-only P9IN Port 9 Input 0 8 read-only PEOUT PEOUT Port E Output 0x82 16 read-write n 0x0 0x0 P10OUT Port 10 Output 8 8 read-write P9OUT Port 9 Output 0 8 read-write PEREN PEREN Port E Resistor Enable 0x86 16 read-write n 0x0 0xFFFF P10REN Port 10 Resistor Enable 8 8 read-write P9REN Port 9 Resistor Enable 0 8 read-write PESEL0 PESEL0 Port E Select 0 0x8A 16 read-write n 0x0 0xFFFF P10SEL0 Port 10 Select 0 8 8 read-write P9SEL0 Port 9 Select 0 0 8 read-write PESEL1 PESEL1 Port E Select 1 0x8C 16 read-write n 0x0 0xFFFF P10SEL1 Port 10 Select 1 8 8 read-write P9SEL1 Port 9 Select 1 0 8 read-write PESELC PESELC Port E Complement Select 0x96 16 read-write n 0x0 0xFFFF P10SELC Port 10 Complement Select 8 8 read-write P9SELC Port 9 Complement Select 0 8 read-write PJDIR PJDIR Port J Direction 0x124 16 read-write n 0x0 0xFFFF PJDIR Port J Direction 0 16 read-write PJDS PJDS Port J Drive Strength 0x128 16 read-write n 0x0 0x0 PJDS Port J Drive Strength 0 16 read-write PJIN PJIN Port J Input 0x120 16 read-only n 0x0 0x0 PJIN Port J Input 0 16 read-only PJOUT PJOUT Port J Output 0x122 16 read-write n 0x0 0x0 PJOUT Port J Output 0 16 read-write PJREN PJREN Port J Resistor Enable 0x126 16 read-write n 0x0 0xFFFF PJREN Port J Resistor Enable 0 16 read-write PJSEL0 PJSEL0 Port J Select 0 0x12A 16 read-write n 0x0 0xFFFF PJSEL0 Port J Select 0 0 16 read-write PJSEL1 PJSEL1 Port J Select 1 0x12C 16 read-write n 0x0 0xFFFF PJSEL1 Port J Select 1 0 16 read-write PJSELC PJSELC Port J Complement Select 0x136 16 read-write n 0x0 0xFFFF PJSELC Port J Complement Select 0 16 read-write DMA DMA DMA 0x4000E000 0x0 0x1050 registers n DMA_ERR_IRQ DMA_ERR Interrupt 30 DMA_INT3_IRQ DMA_INT3 Interrupt 31 DMA_INT2_IRQ DMA_INT2 Interrupt 32 DMA_INT1_IRQ DMA_INT1 Interrupt 33 DMA_INT0_IRQ DMA_INT0 Interrupt 34 ALTBASE ALTBASE Channel Alternate Control Data Base Pointer Register 0x100C 32 read-only n 0x0 0xFFFFFF00 ADDR Base address of the alternate data structure 0 32 read-only ALTCLR ALTCLR Channel Primary-Alternate Clear Register 0x1034 32 write-only n 0x0 0x0 CLR Channel Primary-Alternate Clear Register 0 32 write-only CLR_enum_write write CLR_0 No effect. Use the DMA_ALTSET Register to select the alternate data structure. 0 CLR_1 Selects the primary data structure for channel C. Writing to a bit where a DMA channel is not implemented has no effect. 1 ALTSET ALTSET Channel Primary-Alternate Set Register 0x1030 32 read-write n 0x0 0xFFFFFFFF SET Channel Primary-Alternate Set Register 0 32 read-write SET_enum_write write SEL_0_WRITE No effect. Use the DMA_ALTCLR Register to set bit [C] to 0. 0 SET_0_READ DMA channel C is using the primary data structure. 0 SEL_1_WRITE Selects the alternate data structure for channel C. Writing to a bit where a DMA channel is not implemented has no effect. 1 SET_1_READ DMA channel C is using the alternate data structure. 1 CFG CFG Configuration Register 0x1004 32 write-only n 0x0 0x0 CHPROTCTRL Sets the AHB-Lite protection by controlling the HPROT[3:1] signal levels as follows: Bit [7] Controls HPROT[3] to indicate if a cacheable access is occurring. Bit [6] Controls HPROT[2] to indicate if a bufferable access is occurring. Bit [5] Controls HPROT[1] to indicate if a privileged access is occurring. Note: When bit [n] = 1 then the corresponding HPROT is HIGH. When bit [n] = 0 then the corresponding HPROT is LOW. 5 3 write-only MASTEN Enable status of the controller 0 1 write-only MASTEN_enum_write write MASTEN_0 Controller disabled 0 MASTEN_1 Controller enabled 1 CH_SRCCFG0 CH_SRCCFG0 Channel n Source Configuration Register 0x10 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG1 CH_SRCCFG1 Channel n Source Configuration Register 0x14 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG10 CH_SRCCFG10 Channel n Source Configuration Register 0x38 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG11 CH_SRCCFG11 Channel n Source Configuration Register 0x3C 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG12 CH_SRCCFG12 Channel n Source Configuration Register 0x40 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG13 CH_SRCCFG13 Channel n Source Configuration Register 0x44 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG14 CH_SRCCFG14 Channel n Source Configuration Register 0x48 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG15 CH_SRCCFG15 Channel n Source Configuration Register 0x4C 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG16 CH_SRCCFG16 Channel n Source Configuration Register 0x50 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG17 CH_SRCCFG17 Channel n Source Configuration Register 0x54 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG18 CH_SRCCFG18 Channel n Source Configuration Register 0x58 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG19 CH_SRCCFG19 Channel n Source Configuration Register 0x5C 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG2 CH_SRCCFG2 Channel n Source Configuration Register 0x18 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG20 CH_SRCCFG20 Channel n Source Configuration Register 0x60 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG21 CH_SRCCFG21 Channel n Source Configuration Register 0x64 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG22 CH_SRCCFG22 Channel n Source Configuration Register 0x68 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG23 CH_SRCCFG23 Channel n Source Configuration Register 0x6C 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG24 CH_SRCCFG24 Channel n Source Configuration Register 0x70 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG25 CH_SRCCFG25 Channel n Source Configuration Register 0x74 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG26 CH_SRCCFG26 Channel n Source Configuration Register 0x78 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG27 CH_SRCCFG27 Channel n Source Configuration Register 0x7C 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG28 CH_SRCCFG28 Channel n Source Configuration Register 0x80 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG29 CH_SRCCFG29 Channel n Source Configuration Register 0x84 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG3 CH_SRCCFG3 Channel n Source Configuration Register 0x1C 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG30 CH_SRCCFG30 Channel n Source Configuration Register 0x88 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG31 CH_SRCCFG31 Channel n Source Configuration Register 0x8C 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG4 CH_SRCCFG4 Channel n Source Configuration Register 0x20 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG5 CH_SRCCFG5 Channel n Source Configuration Register 0x24 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG6 CH_SRCCFG6 Channel n Source Configuration Register 0x28 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG7 CH_SRCCFG7 Channel n Source Configuration Register 0x2C 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG8 CH_SRCCFG8 Channel n Source Configuration Register 0x30 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG9 CH_SRCCFG9 Channel n Source Configuration Register 0x34 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[0] CH_SRCCFG[%s] Channel n Source Configuration Register 0x20 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[10] CH_SRCCFG[%s] Channel n Source Configuration Register 0x19C 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[11] CH_SRCCFG[%s] Channel n Source Configuration Register 0x1D8 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[12] CH_SRCCFG[%s] Channel n Source Configuration Register 0x218 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[13] CH_SRCCFG[%s] Channel n Source Configuration Register 0x25C 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[14] CH_SRCCFG[%s] Channel n Source Configuration Register 0x2A4 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[15] CH_SRCCFG[%s] Channel n Source Configuration Register 0x2F0 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[16] CH_SRCCFG[%s] Channel n Source Configuration Register 0x340 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[17] CH_SRCCFG[%s] Channel n Source Configuration Register 0x394 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[18] CH_SRCCFG[%s] Channel n Source Configuration Register 0x3EC 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[19] CH_SRCCFG[%s] Channel n Source Configuration Register 0x448 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[1] CH_SRCCFG[%s] Channel n Source Configuration Register 0x34 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[20] CH_SRCCFG[%s] Channel n Source Configuration Register 0x4A8 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[21] CH_SRCCFG[%s] Channel n Source Configuration Register 0x50C 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[22] CH_SRCCFG[%s] Channel n Source Configuration Register 0x574 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[23] CH_SRCCFG[%s] Channel n Source Configuration Register 0x5E0 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[24] CH_SRCCFG[%s] Channel n Source Configuration Register 0x650 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[25] CH_SRCCFG[%s] Channel n Source Configuration Register 0x6C4 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[26] CH_SRCCFG[%s] Channel n Source Configuration Register 0x73C 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[27] CH_SRCCFG[%s] Channel n Source Configuration Register 0x7B8 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[28] CH_SRCCFG[%s] Channel n Source Configuration Register 0x838 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[29] CH_SRCCFG[%s] Channel n Source Configuration Register 0x8BC 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[2] CH_SRCCFG[%s] Channel n Source Configuration Register 0x4C 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[30] CH_SRCCFG[%s] Channel n Source Configuration Register 0x944 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[31] CH_SRCCFG[%s] Channel n Source Configuration Register 0x9D0 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[3] CH_SRCCFG[%s] Channel n Source Configuration Register 0x68 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[4] CH_SRCCFG[%s] Channel n Source Configuration Register 0x88 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[5] CH_SRCCFG[%s] Channel n Source Configuration Register 0xAC 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[6] CH_SRCCFG[%s] Channel n Source Configuration Register 0xD4 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[7] CH_SRCCFG[%s] Channel n Source Configuration Register 0x100 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[8] CH_SRCCFG[%s] Channel n Source Configuration Register 0x130 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CH_SRCCFG[9] CH_SRCCFG[%s] Channel n Source Configuration Register 0x164 32 read-write n 0x0 0xFFFFFFFF DMA_SRC Device level DMA source mapping to channel input 0 8 read-write CTLBASE CTLBASE Channel Control Data Base Pointer Register 0x1008 32 read-write n 0x0 0xFFFFFFFF ADDR Pointer to the base address of the primary data structure. 5 27 read-write DEVICE_CFG DEVICE_CFG Device Configuration Status 0x0 32 read-only n 0x0 0xFFFF0000 NUM_DMA_CHANNELS Number of DMA channels available 0 8 read-only NUM_SRC_PER_CHANNEL Number of DMA sources per channel 8 8 read-only ENACLR ENACLR Channel Enable Clear Register 0x102C 32 write-only n 0x0 0x0 CLR Set the appropriate bit to disable the corresponding DMA channel. Note: The controller disables a channel, by setting the appropriate bit, when: a) it completes the DMA cycle b) it reads a channel_cfg memory location which has cycle_ctrl = b000 c) an ERROR occurs on the AHB-Lite bus. 0 32 write-only CLR_enum_write write CLR_0 No effect. Use the DMA_ENASET Register to enable DMA channels. 0 CLR_1 Disables channel C. Writing to a bit where a DMA channel is not implemented has no effect. 1 ENASET ENASET Channel Enable Set Register 0x1028 32 read-write n 0x0 0xFFFFFFFF SET Returns the enable status of the channels, or enables the corresponding channels. 0 32 read-write SET_enum_write write SET_0_WRITE No effect. Use the DMA_ENACLR Register to disable a channel. 0 SET_0_READ Channel C is disabled. 0 SET_1_WRITE Enables channel C. Writing to a bit where a DMA channel is not implemented has no effect. 1 SET_1_READ Channel C is enabled. 1 ERRCLR ERRCLR Bus Error Clear Register 0x104C 32 read-write n 0x0 0xFFFFFFFF ERRCLR Returns the status of dma_err, or sets the signal LOW. For test purposes, use the ERRSET register to set dma_err HIGH. Note: If you deassert dma_err at the same time as an ERROR occurs on the AHB-Lite bus, then the ERROR condition takes precedence and dma_err remains asserted. 0 1 read-write ERRCLR_enum_write write ERRCLR_0_WRITE No effect, status of dma_err is unchanged. 0 ERRCLR_0_READ dma_err is LOW 0 ERRCLR_1_WRITE Sets dma_err LOW. 1 ERRCLR_1_READ dma_err is HIGH. 1 INT0_CLRFLG INT0_CLRFLG Interrupt 0 Source Channel Clear Flag Register 0x114 32 write-only n 0x0 0x0 CH0 Clear corresponding DMA_INT0_SRCFLG_REG 0 1 write-only CH1 Clear corresponding DMA_INT0_SRCFLG_REG 1 1 write-only CH10 Clear corresponding DMA_INT0_SRCFLG_REG 10 1 write-only CH11 Clear corresponding DMA_INT0_SRCFLG_REG 11 1 write-only CH12 Clear corresponding DMA_INT0_SRCFLG_REG 12 1 write-only CH13 Clear corresponding DMA_INT0_SRCFLG_REG 13 1 write-only CH14 Clear corresponding DMA_INT0_SRCFLG_REG 14 1 write-only CH15 Clear corresponding DMA_INT0_SRCFLG_REG 15 1 write-only CH16 Clear corresponding DMA_INT0_SRCFLG_REG 16 1 write-only CH17 Clear corresponding DMA_INT0_SRCFLG_REG 17 1 write-only CH18 Clear corresponding DMA_INT0_SRCFLG_REG 18 1 write-only CH19 Clear corresponding DMA_INT0_SRCFLG_REG 19 1 write-only CH2 Clear corresponding DMA_INT0_SRCFLG_REG 2 1 write-only CH20 Clear corresponding DMA_INT0_SRCFLG_REG 20 1 write-only CH21 Clear corresponding DMA_INT0_SRCFLG_REG 21 1 write-only CH22 Clear corresponding DMA_INT0_SRCFLG_REG 22 1 write-only CH23 Clear corresponding DMA_INT0_SRCFLG_REG 23 1 write-only CH24 Clear corresponding DMA_INT0_SRCFLG_REG 24 1 write-only CH25 Clear corresponding DMA_INT0_SRCFLG_REG 25 1 write-only CH26 Clear corresponding DMA_INT0_SRCFLG_REG 26 1 write-only CH27 Clear corresponding DMA_INT0_SRCFLG_REG 27 1 write-only CH28 Clear corresponding DMA_INT0_SRCFLG_REG 28 1 write-only CH29 Clear corresponding DMA_INT0_SRCFLG_REG 29 1 write-only CH3 Clear corresponding DMA_INT0_SRCFLG_REG 3 1 write-only CH30 Clear corresponding DMA_INT0_SRCFLG_REG 30 1 write-only CH31 Clear corresponding DMA_INT0_SRCFLG_REG 31 1 write-only CH4 Clear corresponding DMA_INT0_SRCFLG_REG 4 1 write-only CH5 Clear corresponding DMA_INT0_SRCFLG_REG 5 1 write-only CH6 Clear corresponding DMA_INT0_SRCFLG_REG 6 1 write-only CH7 Clear corresponding DMA_INT0_SRCFLG_REG 7 1 write-only CH8 Clear corresponding DMA_INT0_SRCFLG_REG 8 1 write-only CH9 Clear corresponding DMA_INT0_SRCFLG_REG 9 1 write-only INT0_SRCFLG INT0_SRCFLG Interrupt 0 Source Channel Flag Register 0x110 32 read-only n 0x0 0xFFFFFFFF CH0 Channel 0 was the source of DMA_INT0 0 1 read-only CH1 Channel 1 was the source of DMA_INT0 1 1 read-only CH10 Channel 10 was the source of DMA_INT0 10 1 read-only CH11 Channel 11 was the source of DMA_INT0 11 1 read-only CH12 Channel 12 was the source of DMA_INT0 12 1 read-only CH13 Channel 13 was the source of DMA_INT0 13 1 read-only CH14 Channel 14 was the source of DMA_INT0 14 1 read-only CH15 Channel 15 was the source of DMA_INT0 15 1 read-only CH16 Channel 16 was the source of DMA_INT0 16 1 read-only CH17 Channel 17 was the source of DMA_INT0 17 1 read-only CH18 Channel 18 was the source of DMA_INT0 18 1 read-only CH19 Channel 19 was the source of DMA_INT0 19 1 read-only CH2 Channel 2 was the source of DMA_INT0 2 1 read-only CH20 Channel 20 was the source of DMA_INT0 20 1 read-only CH21 Channel 21 was the source of DMA_INT0 21 1 read-only CH22 Channel 22 was the source of DMA_INT0 22 1 read-only CH23 Channel 23 was the source of DMA_INT0 23 1 read-only CH24 Channel 24 was the source of DMA_INT0 24 1 read-only CH25 Channel 25 was the source of DMA_INT0 25 1 read-only CH26 Channel 26 was the source of DMA_INT0 26 1 read-only CH27 Channel 27 was the source of DMA_INT0 27 1 read-only CH28 Channel 28 was the source of DMA_INT0 28 1 read-only CH29 Channel 29 was the source of DMA_INT0 29 1 read-only CH3 Channel 3 was the source of DMA_INT0 3 1 read-only CH30 Channel 30 was the source of DMA_INT0 30 1 read-only CH31 Channel 31 was the source of DMA_INT0 31 1 read-only CH4 Channel 4 was the source of DMA_INT0 4 1 read-only CH5 Channel 5 was the source of DMA_INT0 5 1 read-only CH6 Channel 6 was the source of DMA_INT0 6 1 read-only CH7 Channel 7 was the source of DMA_INT0 7 1 read-only CH8 Channel 8 was the source of DMA_INT0 8 1 read-only CH9 Channel 9 was the source of DMA_INT0 9 1 read-only INT1_SRCCFG INT1_SRCCFG Interrupt 1 Source Channel Configuration 0x100 32 read-write n 0x0 0xFFFFFFFF EN Enables DMA_INT1 mapping 5 1 read-write INT_SRC Controls which channel's completion event is mapped as a source of this Interrupt 0 5 read-write INT2_SRCCFG INT2_SRCCFG Interrupt 2 Source Channel Configuration Register 0x104 32 read-write n 0x0 0xFFFFFFFF EN Enables DMA_INT2 mapping 5 1 read-write INT_SRC Controls which channel's completion event is mapped as a source of this Interrupt 0 5 read-write INT3_SRCCFG INT3_SRCCFG Interrupt 3 Source Channel Configuration Register 0x108 32 read-write n 0x0 0xFFFFFFFF EN Enables DMA_INT3 mapping 5 1 read-write INT_SRC Controls which channel's completion event is mapped as a source of this Interrupt 0 5 read-write PRIOCLR PRIOCLR Channel Priority Clear Register 0x103C 32 write-only n 0x0 0x0 CLR Set the appropriate bit to select the default priority level for the specified DMA channel. 0 32 write-only CLR_enum_write write CLR_0 No effect. Use the DMA_PRIOSET Register to set channel C to the high priority level. 0 CLR_1 Channel C uses the default priority level. Writing to a bit where a DMA channel is not implemented has no effect. 1 PRIOSET PRIOSET Channel Priority Set Register 0x1038 32 read-write n 0x0 0xFFFFFFFF SET Returns the channel priority mask status, or sets the channel priority to high. 0 32 read-write SET_enum_write write SET_0_WRITE No effect. Use the DMA_PRIOCLR Register to set channel C to the default priority level. 0 SET_0_READ DMA channel C is using the default priority level. 0 SET_1_WRITE Channel C uses the high priority level. Writing to a bit where a DMA channel is not implemented has no effect. 1 SET_1_READ DMA channel C is using a high priority level. 1 REQMASKCLR REQMASKCLR Channel Request Mask Clear Register 0x1024 32 write-only n 0x0 0x0 CLR Set the appropriate bit to enable DMA requests for the channel corresponding to dma_req and dma_sreq. 0 32 write-only CLR_enum_write write CLR_0 No effect. Use the DMA_REQMASKSET Register to disable dma_req and dma_sreq from generating requests. 0 CLR_1 Enables dma_req[C] or dma_sreq[C] to generate DMA requests. Writing to a bit where a DMA channel is not implemented has no effect. 1 REQMASKSET REQMASKSET Channel Request Mask Set Register 0x1020 32 read-write n 0x0 0xFFFFFFFF SET Returns the request mask status of dma_req and dma_sreq, or disables the corresponding channel from generating DMA requests. 0 32 read-write SET_enum_write write SET_0_WRITE No effect. Use the DMA_REQMASKCLR Register to enable DMA requests. 0 SET_0_READ External requests are enabled for channel C. 0 SET_1_WRITE Disables dma_req[C] and dma_sreq[C] from generating DMA requests. Writing to a bit where a DMA channel is not implemented has no effect. 1 SET_1_READ External requests are disabled for channel C. 1 STAT STAT Status Register 0x1000 32 read-only n 0x0 0xF00FFFF DMACHANS Number of available DMA channels minus one. 16 5 read-only DMACHANS_enum_read read DMACHANS_0 Controller configured to use 1 DMA channel 0 DMACHANS_1 Controller configured to use 2 DMA channels 1 DMACHANS_30 Controller configured to use 31 DMA channels 30 DMACHANS_31 Controller configured to use 32 DMA channels 31 MASTEN Enable status of the controller 0 1 read-only MASTEN_enum_read read MASTEN_0 Controller disabled 0 MASTEN_1 Controller enabled 1 STATE Current state of the control state machine. State can be one of the following: 4 4 read-only STATE_enum_read read STATE_0 idle 0 STATE_1 reading channel controller data 1 STATE_10 peripheral scatter-gather transition 10 STATE_2 reading source data end pointer 2 STATE_3 reading destination data end pointer 3 STATE_4 reading source data 4 STATE_5 writing destination data 5 STATE_6 waiting for DMA request to clear 6 STATE_7 writing channel controller data 7 STATE_8 stalled 8 STATE_9 done 9 TESTSTAT To reduce the gate count the controller can be configured to exclude the integration test logic. The values 2h to Fh are Reserved. 28 4 read-only TESTSTAT_enum_read read TESTSTAT_0 Controller does not include the integration test logic 0 TESTSTAT_1 Controller includes the integration test logic 1 SWREQ SWREQ Channel Software Request Register 0x1014 32 write-only n 0x0 0x0 CHNL_SW_REQ Set the appropriate bit to generate a software DMA request on the corresponding DMA channel. Writing to a bit where a DMA channel is not implemented does not create a DMA request for that channel. 0 32 write-only CHNL_SW_REQ_enum_write write CHNL_SW_REQ_0 Does not create a DMA request for the channel 0 CHNL_SW_REQ_1 Creates a DMA request for the channel 1 SW_CHTRIG SW_CHTRIG Software Channel Trigger Register 0x4 32 read-write n 0x0 0xFFFFFFFF CH0 Write 1, triggers DMA_CHANNEL0 0 1 read-write CH1 Write 1, triggers DMA_CHANNEL1 1 1 read-write CH10 Write 1, triggers DMA_CHANNEL10 10 1 read-write CH11 Write 1, triggers DMA_CHANNEL11 11 1 read-write CH12 Write 1, triggers DMA_CHANNEL12 12 1 read-write CH13 Write 1, triggers DMA_CHANNEL13 13 1 read-write CH14 Write 1, triggers DMA_CHANNEL14 14 1 read-write CH15 Write 1, triggers DMA_CHANNEL15 15 1 read-write CH16 Write 1, triggers DMA_CHANNEL16 16 1 read-write CH17 Write 1, triggers DMA_CHANNEL17 17 1 read-write CH18 Write 1, triggers DMA_CHANNEL18 18 1 read-write CH19 Write 1, triggers DMA_CHANNEL19 19 1 read-write CH2 Write 1, triggers DMA_CHANNEL2 2 1 read-write CH20 Write 1, triggers DMA_CHANNEL20 20 1 read-write CH21 Write 1, triggers DMA_CHANNEL21 21 1 read-write CH22 Write 1, triggers DMA_CHANNEL22 22 1 read-write CH23 Write 1, triggers DMA_CHANNEL23 23 1 read-write CH24 Write 1, triggers DMA_CHANNEL24 24 1 read-write CH25 Write 1, triggers DMA_CHANNEL25 25 1 read-write CH26 Write 1, triggers DMA_CHANNEL26 26 1 read-write CH27 Write 1, triggers DMA_CHANNEL27 27 1 read-write CH28 Write 1, triggers DMA_CHANNEL28 28 1 read-write CH29 Write 1, triggers DMA_CHANNEL29 29 1 read-write CH3 Write 1, triggers DMA_CHANNEL3 3 1 read-write CH30 Write 1, triggers DMA_CHANNEL30 30 1 read-write CH31 Write 1, triggers DMA_CHANNEL31 31 1 read-write CH4 Write 1, triggers DMA_CHANNEL4 4 1 read-write CH5 Write 1, triggers DMA_CHANNEL5 5 1 read-write CH6 Write 1, triggers DMA_CHANNEL6 6 1 read-write CH7 Write 1, triggers DMA_CHANNEL7 7 1 read-write CH8 Write 1, triggers DMA_CHANNEL8 8 1 read-write CH9 Write 1, triggers DMA_CHANNEL9 9 1 read-write USEBURSTCLR USEBURSTCLR Channel Useburst Clear Register 0x101C 32 write-only n 0x0 0x0 CLR Set the appropriate bit to enable dma_sreq to generate requests. 0 32 write-only CLR_enum_write write CLR_0 No effect. Use the DMA_USEBURST_SET Register to disable dma_sreq from generating requests. 0 CLR_1 Enables dma_sreq[C] to generate DMA requests. Writing to a bit where a DMA channel is not implemented has no effect. 1 USEBURSTSET USEBURSTSET Channel Useburst Set Register 0x1018 32 read-write n 0x0 0xFFFFFFFF SET Returns the useburst status, or disables dma_sreq from generating DMA requests. 0 32 read-write SET_enum_write write SET_0_WRITE No effect. Use the DMA_USEBURST_CLR Register to set bit [C] to 0. 0 SET_0_READ DMA channel C responds to requests that it receives on dma_req[C] or dma_sreq[C]. The controller performs 2R, or single, bus transfers. 0 SET_1_WRITE Disables dma_sreq[C] from generating DMA requests. The controller performs 2R transfers. Writing to a bit where a DMA channel is not implemented has no effect. 1 SET_1_READ DMA channel C does not respond to requests that it receives on dma_sreq[C]. The controller only responds to dma_req[C] requests and performs 2R transfers. 1 WAITSTAT WAITSTAT Channel Wait on Request Status Register 0x1010 32 read-only n 0x0 0xFFFFFFFF WAITREQ Channel wait on request status. 0 32 read-only WAITREQ_enum_read read WAITREQ_0 dma_waitonreq[C] is LOW. 0 WAITREQ_1 dma_waitonreq[C] is HIGH. 1 DWT DWT DWT 0xE0001000 0x0 0x1000 registers n COMP0 COMP0 DWT Comparator Register 0 0x20 32 read-write n 0x0 0x0 COMP Data value to compare against PC and the data address as given by DWT_FUNCTION0. DWT_COMP0 can also compare against the value of the PC Sampler Counter (DWT_CYCCNT). 0 32 read-write COMP1 COMP1 DWT Comparator Register 1 0x30 32 read-write n 0x0 0x0 COMP Data value to compare against PC and the data address as given by DWT_FUNCTION1. 0 32 read-write COMP2 COMP2 DWT Comparator Register 2 0x40 32 read-write n 0x0 0x0 COMP Data value to compare against PC and the data address as given by DWT_FUNCTION2. 0 32 read-write COMP3 COMP3 DWT Comparator Register 3 0x50 32 read-write n 0x0 0x0 COMP Data value to compare against PC and the data address as given by DWT_FUNCTION3. 0 32 read-write CPICNT CPICNT DWT CPI Count Register 0x8 32 read-write n 0x0 0x0 CPICNT Current CPI counter value. Increments on the additional cycles (the first cycle is not counted) required to execute all instructions except those recorded by DWT_LSUCNT. This counter also increments on all instruction fetch stalls. If CPIEVTENA is set, an event is emitted when the counter overflows. Clears to 0 on enabling. 0 8 read-write CTRL CTRL DWT Control Register 0x0 32 read-write n 0x40000000 0x0 CPIEVTENA Enables CPI count event. Emits an event when DWT_CPICNT overflows (every 256 cycles of multi-cycle instructions). Reset clears the CPIEVTENA bit. 17 1 read-write en_0b0 CPI counter events disabled. 0 en_0b1 CPI counter events enabled. 1 CYCCNTENA Enable the CYCCNT counter. If not enabled, the counter does not count and no event is generated for PS sampling or CYCCNTENA. In normal use, the debugger must initialize the CYCCNT counter to 0. 0 1 read-write CYCEVTENA Enables Cycle count event. Emits an event when the POSTCNT counter triggers it. See CYCTAP (bit [9]) and POSTPRESET, bits [4:1], for details. This event is only emitted if PCSAMPLENA, bit [12], is disabled. PCSAMPLENA overrides the setting of this bit. Reset clears the CYCEVTENA bit. 22 1 read-write en_0b0 Cycle count events disabled. 0 en_0b1 Cycle count events enabled. 1 CYCTAP Selects a tap on the DWT_CYCCNT register. These are spaced at bits [6] and [10]. When the selected bit in the CYCCNT register changes from 0 to 1 or 1 to 0, it emits into the POSTCNT, bits [8:5], post-scalar counter. That counter then counts down. On a bit change when post-scalar is 0, it triggers an event for PC sampling or CYCEVTCNT. 9 1 read-write en_0b0 selects bit [6] to tap 0 en_0b1 selects bit [10] to tap. 1 EXCEVTENA Enables Interrupt overhead event. Emits an event when DWT_EXCCNT overflows (every 256 cycles of interrupt overhead). Reset clears the EXCEVTENA bit. 18 1 read-write en_0b0 Interrupt overhead event disabled. 0 en_0b1 Interrupt overhead event enabled. 1 EXCTRCENA Enables Interrupt event tracing. Reset clears the EXCEVTENA bit. 16 1 read-write en_0b0 interrupt event trace disabled. 0 en_0b1 interrupt event trace enabled. 1 FOLDEVTENA Enables Folded instruction count event. Emits an event when DWT_FOLDCNT overflows (every 256 cycles of folded instructions). A folded instruction is one that does not incur even one cycle to execute. For example, an IT instruction is folded away and so does not use up one cycle. Reset clears the FOLDEVTENA bit. 21 1 read-write en_0b0 Folded instruction count events disabled. 0 en_0b1 Folded instruction count events enabled. 1 LSUEVTENA Enables LSU count event. Emits an event when DWT_LSUCNT overflows (every 256 cycles of LSU operation). LSU counts include all LSU costs after the initial cycle for the instruction. Reset clears the LSUEVTENA bit. 20 1 read-write en_0b0 LSU count events disabled. 0 en_0b1 LSU count events enabled. 1 NOCYCCNT When set, DWT_CYCCNT is not supported. 25 1 read-write NOPRFCNT When set, DWT_FOLDCNT, DWT_LSUCNT, DWT_SLEEPCNT, DWT_EXCCNT, and DWT_CPICNT are not supported. 24 1 read-write PCSAMPLEENA Enables PC Sampling event. A PC sample event is emitted when the POSTCNT counter triggers it. See CYCTAP, bit [9], and POSTPRESET, bits [4:1], for details. Enabling this bit overrides CYCEVTENA (bit [20]). Reset clears the PCSAMPLENA bit. 12 1 read-write en_0b0 PC Sampling event disabled. 0 en_0b1 Sampling event enabled. 1 POSTCNT Post-scalar counter for CYCTAP. When the selected tapped bit changes from 0 to 1 or 1 to 0, the post scalar counter is down-counted when not 0. If 0, it triggers an event for PCSAMPLENA or CYCEVTENA use. It also reloads with the value from POSTPRESET (bits [4:1]). 5 4 read-write POSTPRESET Reload value for POSTCNT, bits [8:5], post-scalar counter. If this value is 0, events are triggered on each tap change (a power of 2). If this field has a non-0 value, this forms a count-down value, to be reloaded into POSTCNT each time it reaches 0. For example, a value 1 in this register means an event is formed every other tap change. 1 4 read-write SLEEPEVTENA Enables Sleep count event. Emits an event when DWT_SLEEPCNT overflows (every 256 cycles that the processor is sleeping). Reset clears the SLEEPEVTENA bit. 19 1 read-write en_0b0 Sleep count events disabled. 0 en_0b1 Sleep count events enabled. 1 SYNCTAP Feeds a synchronization pulse to the ITM SYNCENA control. The value selected here picks the rate (approximately 1/second or less) by selecting a tap on the DWT_CYCCNT register. To use synchronization (heartbeat and hot-connect synchronization), CYCCNTENA must be set to 1, SYNCTAP must be set to one of its values, and SYNCENA must be set to 1. 10 2 read-write en_0b00 Disabled. No synch counting. 0 en_0b01 Tap at CYCCNT bit 24. 1 en_0b10 Tap at CYCCNT bit 26. 2 en_0b11 Tap at CYCCNT bit 28. 3 CYCCNT CYCCNT DWT Current PC Sampler Cycle Count Register 0x4 32 read-write n 0x0 0x0 CYCCNT Current PC Sampler Cycle Counter count value. When enabled, this counter counts the number of core cycles, except when the core is halted. CYCCNT is a free running counter, counting upwards. It wraps around to 0 on overflow. The debugger must initialize this to 0 when first enabling. 0 32 read-write EXCCNT EXCCNT DWT Exception Overhead Count Register 0xC 32 read-write n 0x0 0x0 EXCCNT Current interrupt overhead counter value. Counts the total cycles spent in interrupt processing (for example entry stacking, return unstacking, pre-emption). An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when enabled. Clears to 0 on enabling. 0 8 read-write FOLDCNT FOLDCNT DWT Fold Count Register 0x18 32 read-write n 0x0 0x0 FOLDCNT This counts the total number folded instructions. This counter initializes to 0 when enabled. 0 8 read-write FUNCTION0 FUNCTION0 DWT Function Register 0 0x28 32 read-write n 0x0 0x0 DATAVADDR0 Identity of a linked address comparator for data value matching when DATAVMATCH == 1. 12 4 read-write DATAVADDR1 Identity of a second linked address comparator for data value matching when DATAVMATCH == 1 and LNK1ENA == 1. 16 4 read-write DATAVMATCH This bit is only available in comparator 1. When DATAVMATCH is set, this comparator performs data value compares. The comparators given by DATAVADDR0 and DATAVADDR1provide the address for the data comparison. If DATAVMATCH is set in DWT_FUNCTION1, the FUNCTION setting for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and those comparators only provide the address match for the data comparison. 8 1 read-write DATAVSIZE Defines the size of the data in the COMP register that is to be matched: 10 2 read-write en_0b00 byte 0 en_0b01 halfword 1 en_0b10 word 2 en_0b11 Unpredictable. 3 EMITRANGE Emit range field. Reserved to permit emitting offset when range match occurs. Reset clears the EMITRANGE bit. PC sampling is not supported when EMITRANGE is enabled. EMITRANGE only applies for: FUNCTION = b0001, b0010, b0011, b1100, b1101, b1110, and b1111. 5 1 read-write FUNCTION Function settings. Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. 0 4 read-write en_0b0000 Disabled 0 en_0b0001 EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM 1 en_0b1010 ETM trigger on write 10 en_0b1011 ETM trigger on read or write 11 en_0b1100 EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers 12 en_0b1101 EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers 13 en_0b1110 EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers 14 en_0b1111 EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers 15 en_0b0010 EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. 2 en_0b0011 EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. 3 en_0b0100 Watchpoint on PC match. 4 en_0b0101 Watchpoint on read. 5 en_0b0110 Watchpoint on write. 6 en_0b0111 Watchpoint on read or write. 7 en_0b1000 ETM trigger on PC match 8 en_0b1001 ETM trigger on read 9 LNK1ENA 9 1 read-only en_0b0 DATAVADDR1 not supported 0 en_0b1 DATAVADDR1 supported (enabled). 1 MATCHED This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read. 24 1 read-write FUNCTION1 FUNCTION1 DWT Function Register 1 0x38 32 read-write n 0x0 0x0 CYCMATCH Only available in comparator 0. When set, this comparator compares against the clock cycle counter. 7 1 read-write DATAVADDR0 Identity of a linked address comparator for data value matching when DATAVMATCH == 1. 12 4 read-write DATAVADDR1 Identity of a second linked address comparator for data value matching when DATAVMATCH == 1 and LNK1ENA == 1. 16 4 read-write DATAVMATCH This bit is only available in comparator 1. When DATAVMATCH is set, this comparator performs data value compares. The comparators given by DATAVADDR0 and DATAVADDR1provide the address for the data comparison. If DATAVMATCH is set in DWT_FUNCTION1, the FUNCTION setting for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and those comparators only provide the address match for the data comparison. 8 1 read-write DATAVSIZE Defines the size of the data in the COMP register that is to be matched: 10 2 read-write en_0b00 byte 0 en_0b01 halfword 1 en_0b10 word 2 en_0b11 Unpredictable. 3 EMITRANGE Emit range field. Reserved to permit emitting offset when range match occurs. Reset clears the EMITRANGE bit. PC sampling is not supported when EMITRANGE is enabled. EMITRANGE only applies for: FUNCTION = b0001, b0010, b0011, b1100, b1101, b1110, and b1111. 5 1 read-write FUNCTION Function settings. Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: FUNCTION is overridden for comparators given by DATAVADDR0 and DATAVADDR1 in DWT_FUNCTION1if DATAVMATCH is also set in DWT_FUNCTION1. The comparators given by DATAVADDR0 and DATAVADDR1 can then only perform address comparator matches for comparator 1 data matches. Note 4: If the data matching functionality is not included during implementation it is not possible to set DATAVADDR0, DATAVADDR1, or DATAVMATCH in DWT_FUNCTION1. This means that the data matching functionality is not available in the implementation. Test the availability of data matching by writing and reading the DATAVMATCH bit in DWT_FUNCTION1. If it is not settable then data matching is unavailable. Note 5: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. 0 4 read-write en_0b0000 Disabled 0 en_0b0001 EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM 1 en_0b1010 ETM trigger on write 10 en_0b1011 ETM trigger on read or write 11 en_0b1100 EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers 12 en_0b1101 EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers 13 en_0b1110 EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers 14 en_0b1111 EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers 15 en_0b0010 EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. 2 en_0b0011 EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. 3 en_0b0100 Watchpoint on PC match. 4 en_0b0101 Watchpoint on read. 5 en_0b0110 Watchpoint on write. 6 en_0b0111 Watchpoint on read or write. 7 en_0b1000 ETM trigger on PC match 8 en_0b1001 ETM trigger on read 9 LNK1ENA 9 1 read-only en_0b0 DATAVADDR1 not supported 0 en_0b1 DATAVADDR1 supported (enabled). 1 MATCHED This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read. 24 1 read-write FUNCTION2 FUNCTION2 DWT Function Register 2 0x48 32 read-write n 0x0 0x0 DATAVADDR0 Identity of a linked address comparator for data value matching when DATAVMATCH == 1. 12 4 read-write DATAVADDR1 Identity of a second linked address comparator for data value matching when DATAVMATCH == 1 and LNK1ENA == 1. 16 4 read-write DATAVMATCH This bit is only available in comparator 1. When DATAVMATCH is set, this comparator performs data value compares. The comparators given by DATAVADDR0 and DATAVADDR1provide the address for the data comparison. If DATAVMATCH is set in DWT_FUNCTION1, the FUNCTION setting for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and those comparators only provide the address match for the data comparison. 8 1 read-write DATAVSIZE Defines the size of the data in the COMP register that is to be matched: 10 2 read-write en_0b00 byte 0 en_0b01 halfword 1 en_0b10 word 2 en_0b11 Unpredictable. 3 EMITRANGE Emit range field. Reserved to permit emitting offset when range match occurs. Reset clears the EMITRANGE bit. PC sampling is not supported when EMITRANGE is enabled. EMITRANGE only applies for: FUNCTION = b0001, b0010, b0011, b1100, b1101, b1110, and b1111. 5 1 read-write FUNCTION Function settings. Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. 0 4 read-write en_0b0000 Disabled 0 en_0b0001 EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM 1 en_0b1010 ETM trigger on write 10 en_0b1011 ETM trigger on read or write 11 en_0b1100 EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers 12 en_0b1101 EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers 13 en_0b1110 EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers 14 en_0b1111 EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers 15 en_0b0010 EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. 2 en_0b0011 EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. 3 en_0b0100 Watchpoint on PC match. 4 en_0b0101 Watchpoint on read. 5 en_0b0110 Watchpoint on write. 6 en_0b0111 Watchpoint on read or write. 7 en_0b1000 ETM trigger on PC match 8 en_0b1001 ETM trigger on read 9 LNK1ENA 9 1 read-only en_0b0 DATAVADDR1 not supported 0 en_0b1 DATAVADDR1 supported (enabled). 1 MATCHED This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read. 24 1 read-write FUNCTION3 FUNCTION3 DWT Function Register 3 0x58 32 read-write n 0x0 0x0 DATAVADDR0 Identity of a linked address comparator for data value matching when DATAVMATCH == 1. 12 4 read-write DATAVADDR1 Identity of a second linked address comparator for data value matching when DATAVMATCH == 1 and LNK1ENA == 1. 16 4 read-write DATAVMATCH This bit is only available in comparator 1. When DATAVMATCH is set, this comparator performs data value compares. The comparators given by DATAVADDR0 and DATAVADDR1provide the address for the data comparison. If DATAVMATCH is set in DWT_FUNCTION1, the FUNCTION setting for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and those comparators only provide the address match for the data comparison. 8 1 read-write DATAVSIZE Defines the size of the data in the COMP register that is to be matched: 10 2 read-write en_0b00 byte 0 en_0b01 halfword 1 en_0b10 word 2 en_0b11 Unpredictable. 3 EMITRANGE Emit range field. Reserved to permit emitting offset when range match occurs. Reset clears the EMITRANGE bit. PC sampling is not supported when EMITRANGE is enabled. EMITRANGE only applies for: FUNCTION = b0001, b0010, b0011, b1100, b1101, b1110, and b1111. 5 1 read-write FUNCTION Function settings. Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. 0 4 read-write en_0b0000 Disabled 0 en_0b0001 EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM 1 en_0b1010 ETM trigger on write 10 en_0b1011 ETM trigger on read or write 11 en_0b1100 EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers 12 en_0b1101 EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers 13 en_0b1110 EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers 14 en_0b1111 EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers 15 en_0b0010 EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. 2 en_0b0011 EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. 3 en_0b0100 Watchpoint on PC match. 4 en_0b0101 Watchpoint on read. 5 en_0b0110 Watchpoint on write. 6 en_0b0111 Watchpoint on read or write. 7 en_0b1000 ETM trigger on PC match 8 en_0b1001 ETM trigger on read 9 LNK1ENA 9 1 read-only en_0b0 DATAVADDR1 not supported 0 en_0b1 DATAVADDR1 supported (enabled). 1 MATCHED This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read. 24 1 read-write LSUCNT LSUCNT DWT LSU Count Register 0x14 32 read-write n 0x0 0x0 LSUCNT LSU counter. This counts the total number of cycles that the processor is processing an LSU operation. The initial execution cost of the instruction is not counted. For example, an LDR that takes two cycles to complete increments this counter one cycle. Equivalently, an LDR that stalls for two cycles (and so takes four cycles), increments this counter three times. An event is emitted on counter overflow (every 256 cycles). Clears to 0 on enabling. 0 8 read-write MASK0 MASK0 DWT Mask Register 0 0x24 32 read-write n 0x0 0x0 MASK Mask on data address when matching against COMP. This is the size of the ignore mask. hat is, DWT matching is performed as:(ADDR ANDed with (~0 left bit-shifted by MASK)) == COMP. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP is 3, this matches a word access of 0, because 3 would be within the word. 0 4 read-write MASK1 MASK1 DWT Mask Register 1 0x34 32 read-write n 0x0 0x0 MASK Mask on data address when matching against COMP. This is the size of the ignore mask. hat is, DWT matching is performed as:(ADDR ANDed with (~0 left bit-shifted by MASK)) == COMP. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP is 3, this matches a word access of 0, because 3 would be within the word. 0 4 read-write MASK2 MASK2 DWT Mask Register 2 0x44 32 read-write n 0x0 0x0 MASK Mask on data address when matching against COMP. This is the size of the ignore mask. hat is, DWT matching is performed as:(ADDR ANDed with (~0 left bit-shifted by MASK)) == COMP. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP is 3, this matches a word access of 0, because 3 would be within the word. 0 4 read-write MASK3 MASK3 DWT Mask Register 3 0x54 32 read-write n 0x0 0x0 MASK Mask on data address when matching against COMP. This is the size of the ignore mask. hat is, DWT matching is performed as:(ADDR ANDed with (~0 left bit-shifted by MASK)) == COMP. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP is 3, this matches a word access of 0, because 3 would be within the word. 0 4 read-write PCSR PCSR DWT Program Counter Sample Register 0x1C 32 read-only n 0x0 0x0 EIASAMPLE Execution instruction address sample, or 0xFFFFFFFF if the core is halted. 0 32 read-only SLEEPCNT SLEEPCNT DWT Sleep Count Register 0x10 32 read-write n 0x0 0x0 SLEEPCNT Sleep counter. Counts the number of cycles during which the processor is sleeping. An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when enabled. Note that SLEEPCNT is clocked using FCLK. It is possible that the frequency of FCLK might be reduced while the processor is sleeping to minimize power consumption. This means that sleep duration must be calculated with the frequency of FCLK during sleep. 0 8 read-write EUSCI_A0 EUSCI_A0 EUSCI_A0 0x40001000 0x0 0x20 registers n EUSCIA0_IRQ EUSCIA0 Interrupt 16 UCAxABCTL ABCTL eUSCI_Ax Auto Baud Rate Control Register 0x10 16 read-write n 0x0 0xFFFF UCABDEN Automatic baud-rate detect enable 0 1 read-write UCABDEN_0 Baud-rate detection disabled. Length of break and synch field is not measured. 0 UCABDEN_1 Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly. 1 UCBTOE Break time out error 2 1 read-write UCBTOE_0 No error 0 UCBTOE_1 Length of break field exceeded 22 bit times 1 UCDELIM Break/synch delimiter length 4 2 read-write UCDELIM_0 1 bit time 0 UCDELIM_1 2 bit times 1 UCDELIM_2 3 bit times 2 UCDELIM_3 4 bit times 3 UCSTOE Synch field time out error 3 1 read-write UCSTOE_0 No error 0 UCSTOE_1 Length of synch field exceeded measurable time 1 UCAxBRW BRW eUSCI_Ax Baud Rate Control Word Register 0x6 16 read-write n 0x0 0xFF UCBR Clock prescaler setting of the Baud rate generator 0 16 read-write UCAxCTLW0 CTLW0 eUSCI_Ax Control Word Register 0 0x0 16 read-write n 0x1 0xFFFF UC7BIT Character length 12 1 read-write UC7BIT_0 8-bit data 0 UC7BIT_1 7-bit data 1 UCBRKIE Receive break character interrupt enable 4 1 read-write UCBRKIE_0 Received break characters do not set UCRXIFG 0 UCBRKIE_1 Received break characters set UCRXIFG 1 UCDORM Dormant 3 1 read-write UCDORM_0 Not dormant. All received characters set UCRXIFG. 0 UCDORM_1 Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG. 1 UCMODE eUSCI_A mode 9 2 read-write UCMODE_0 UART mode 0 UCMODE_1 Idle-line multiprocessor mode 1 UCMODE_2 Address-bit multiprocessor mode 2 UCMODE_3 UART mode with automatic baud-rate detection 3 UCMSB MSB first select 13 1 read-write UCMSB_0 LSB first 0 UCMSB_1 MSB first 1 UCPAR Parity select 14 1 read-write UCPAR_0 Odd parity 0 UCPAR_1 Even parity 1 UCPEN Parity enable 15 1 read-write UCPEN_0 Parity disabled 0 UCPEN_1 Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation. 1 UCRXEIE Receive erroneous-character interrupt enable 5 1 read-write UCRXEIE_0 Erroneous characters rejected and UCRXIFG is not set 0 UCRXEIE_1 Erroneous characters received set UCRXIFG 1 UCSPB Stop bit select 11 1 read-write UCSPB_0 One stop bit 0 UCSPB_1 Two stop bits 1 UCSSEL eUSCI_A clock source select 6 2 read-write UCSSEL_0 UCLK 0 UCSSEL_1 ACLK 1 UCSSEL_2 SMCLK 2 UCSWRST Software reset enable 0 1 read-write UCSWRST_0 Disabled. eUSCI_A reset released for operation 0 UCSWRST_1 Enabled. eUSCI_A logic held in reset state 1 UCSYNC Synchronous mode enable 8 1 read-write UCSYNC_0 Asynchronous mode 0 UCSYNC_1 Synchronous mode 1 UCTXADDR Transmit address 2 1 read-write UCTXADDR_0 Next frame transmitted is data 0 UCTXADDR_1 Next frame transmitted is an address 1 UCTXBRK Transmit break 1 1 read-write UCTXBRK_0 Next frame transmitted is not a break 0 UCTXBRK_1 Next frame transmitted is a break or a break/synch 1 UCAxCTLW1 CTLW1 eUSCI_Ax Control Word Register 1 0x2 16 read-write n 0x3 0xFFFF UCGLIT Deglitch time 0 2 read-write UCGLIT_0 Approximately 2 ns (equivalent of 1 delay element) 0 UCGLIT_1 Approximately 50 ns 1 UCGLIT_2 Approximately 100 ns 2 UCGLIT_3 Approximately 200 ns 3 UCAxIE IE eUSCI_Ax Interrupt Enable Register 0x1A 16 read-write n 0x0 0xFFFF UCRXIE Receive interrupt enable 0 1 read-write UCRXIE_0 Interrupt disabled 0 UCRXIE_1 Interrupt enabled 1 UCSTTIE Start bit interrupt enable 2 1 read-write UCSTTIE_0 Interrupt disabled 0 UCSTTIE_1 Interrupt enabled 1 UCTXCPTIE Transmit complete interrupt enable 3 1 read-write UCTXCPTIE_0 Interrupt disabled 0 UCTXCPTIE_1 Interrupt enabled 1 UCTXIE Transmit interrupt enable 1 1 read-write UCTXIE_0 Interrupt disabled 0 UCTXIE_1 Interrupt enabled 1 UCAxIFG IFG eUSCI_Ax Interrupt Flag Register 0x1C 16 read-write n 0x2 0xFFFF UCRXIFG Receive interrupt flag 0 1 read-write UCRXIFG_0 No interrupt pending 0 UCRXIFG_1 Interrupt pending 1 UCSTTIFG Start bit interrupt flag 2 1 read-write UCSTTIFG_0 No interrupt pending 0 UCSTTIFG_1 Interrupt pending 1 UCTXCPTIFG Transmit ready interrupt enable 3 1 read-write UCTXCPTIFG_0 No interrupt pending 0 UCTXCPTIFG_1 Interrupt pending 1 UCTXIFG Transmit interrupt flag 1 1 read-write UCTXIFG_0 No interrupt pending 0 UCTXIFG_1 Interrupt pending 1 UCAxIRCTL IRCTL eUSCI_Ax IrDA Control Word Register 0x12 16 read-write n 0x0 0xFFFF UCIREN IrDA encoder/decoder enable 0 1 read-write UCIREN_0 IrDA encoder/decoder disabled 0 UCIREN_1 IrDA encoder/decoder enabled 1 UCIRRXFE IrDA receive filter enabled 8 1 read-write UCIRRXFE_0 Receive filter disabled 0 UCIRRXFE_1 Receive filter enabled 1 UCIRRXFL Receive filter length 10 4 read-write UCIRRXPL IrDA receive input UCAxRXD polarity 9 1 read-write UCIRRXPL_0 IrDA transceiver delivers a high pulse when a light pulse is seen 0 UCIRRXPL_1 IrDA transceiver delivers a low pulse when a light pulse is seen 1 UCIRTXCLK IrDA transmit pulse clock select 1 1 read-write UCIRTXCLK_0 BRCLK 0 UCIRTXCLK_1 BITCLK16 when UCOS16 = 1. Otherwise, BRCLK. 1 UCIRTXPL Transmit pulse length 2 6 read-write UCAxIV IV eUSCI_Ax Interrupt Vector Register 0x1E 16 read-only n 0x0 0xFFFF UCIV eUSCI_A interrupt vector value 0 16 read-only UCIV_enum_read read UCIV_0 No interrupt pending 0 UCIV_2 Interrupt Source: Receive buffer full Interrupt Flag: UCRXIFG Interrupt Priority: Highest 2 UCIV_4 Interrupt Source: Transmit buffer empty Interrupt Flag: UCTXIFG 4 UCIV_6 Interrupt Source: Start bit received Interrupt Flag: UCSTTIFG 6 UCIV_8 Interrupt Source: Transmit complete Interrupt Flag: UCTXCPTIFG Interrupt Priority: Lowest 8 UCAxMCTLW MCTLW eUSCI_Ax Modulation Control Word Register 0x8 16 read-write n 0x0 0xFFFF UCBRF First modulation stage select 4 4 read-write UCBRS Second modulation stage select 8 8 read-write UCOS16 Oversampling mode enabled 0 1 read-write UCOS16_0 Disabled 0 UCOS16_1 Enabled 1 UCAxRXBUF RXBUF eUSCI_Ax Receive Buffer Register 0xC 16 read-only n 0x0 0xFFFF UCRXBUF Receive data buffer 0 8 read-only UCAxSTATW STATW eUSCI_Ax Status Register 0xA 16 read-write n 0x0 0xFFFF UCADDR_UCIDLE Address received / Idle line detected 1 1 read-write UCBRK Break detect flag 3 1 read-write UCBRK_0 No break condition 0 UCBRK_1 Break condition occurred 1 UCBUSY eUSCI_A busy 0 1 read-only UCBUSY_enum_read read UCBUSY_0 eUSCI_A inactive 0 UCBUSY_1 eUSCI_A transmitting or receiving 1 UCFE Framing error flag 6 1 read-write UCFE_0 No error 0 UCFE_1 Character received with low stop bit 1 UCLISTEN Listen enable 7 1 read-write UCLISTEN_0 Disabled 0 UCLISTEN_1 Enabled. UCAxTXD is internally fed back to the receiver 1 UCOE Overrun error flag 5 1 read-write UCOE_0 No error 0 UCOE_1 Overrun error occurred 1 UCPE Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read. 4 1 read-write UCPE_0 No error 0 UCPE_1 Character received with parity error 1 UCRXERR Receive error flag 2 1 read-write UCRXERR_0 No receive errors detected 0 UCRXERR_1 Receive error detected 1 UCAxTXBUF TXBUF eUSCI_Ax Transmit Buffer Register 0xE 16 read-write n 0x0 0xFFFF UCTXBUF Transmit data buffer 0 8 read-write EUSCI_A1 EUSCI_A1 EUSCI_A1 0x40001400 0x0 0x20 registers n EUSCIA1_IRQ EUSCIA1 Interrupt 17 UCAxABCTL ABCTL eUSCI_Ax Auto Baud Rate Control Register 0x10 16 read-write n 0x0 0xFFFF UCABDEN Automatic baud-rate detect enable 0 1 read-write UCABDEN_0 Baud-rate detection disabled. Length of break and synch field is not measured. 0 UCABDEN_1 Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly. 1 UCBTOE Break time out error 2 1 read-write UCBTOE_0 No error 0 UCBTOE_1 Length of break field exceeded 22 bit times 1 UCDELIM Break/synch delimiter length 4 2 read-write UCDELIM_0 1 bit time 0 UCDELIM_1 2 bit times 1 UCDELIM_2 3 bit times 2 UCDELIM_3 4 bit times 3 UCSTOE Synch field time out error 3 1 read-write UCSTOE_0 No error 0 UCSTOE_1 Length of synch field exceeded measurable time 1 UCAxBRW BRW eUSCI_Ax Baud Rate Control Word Register 0x6 16 read-write n 0x0 0xFF UCBR Clock prescaler setting of the Baud rate generator 0 16 read-write UCAxCTLW0 CTLW0 eUSCI_Ax Control Word Register 0 0x0 16 read-write n 0x1 0xFFFF UC7BIT Character length 12 1 read-write UC7BIT_0 8-bit data 0 UC7BIT_1 7-bit data 1 UCBRKIE Receive break character interrupt enable 4 1 read-write UCBRKIE_0 Received break characters do not set UCRXIFG 0 UCBRKIE_1 Received break characters set UCRXIFG 1 UCDORM Dormant 3 1 read-write UCDORM_0 Not dormant. All received characters set UCRXIFG. 0 UCDORM_1 Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG. 1 UCMODE eUSCI_A mode 9 2 read-write UCMODE_0 UART mode 0 UCMODE_1 Idle-line multiprocessor mode 1 UCMODE_2 Address-bit multiprocessor mode 2 UCMODE_3 UART mode with automatic baud-rate detection 3 UCMSB MSB first select 13 1 read-write UCMSB_0 LSB first 0 UCMSB_1 MSB first 1 UCPAR Parity select 14 1 read-write UCPAR_0 Odd parity 0 UCPAR_1 Even parity 1 UCPEN Parity enable 15 1 read-write UCPEN_0 Parity disabled 0 UCPEN_1 Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation. 1 UCRXEIE Receive erroneous-character interrupt enable 5 1 read-write UCRXEIE_0 Erroneous characters rejected and UCRXIFG is not set 0 UCRXEIE_1 Erroneous characters received set UCRXIFG 1 UCSPB Stop bit select 11 1 read-write UCSPB_0 One stop bit 0 UCSPB_1 Two stop bits 1 UCSSEL eUSCI_A clock source select 6 2 read-write UCSSEL_0 UCLK 0 UCSSEL_1 ACLK 1 UCSSEL_2 SMCLK 2 UCSWRST Software reset enable 0 1 read-write UCSWRST_0 Disabled. eUSCI_A reset released for operation 0 UCSWRST_1 Enabled. eUSCI_A logic held in reset state 1 UCSYNC Synchronous mode enable 8 1 read-write UCSYNC_0 Asynchronous mode 0 UCSYNC_1 Synchronous mode 1 UCTXADDR Transmit address 2 1 read-write UCTXADDR_0 Next frame transmitted is data 0 UCTXADDR_1 Next frame transmitted is an address 1 UCTXBRK Transmit break 1 1 read-write UCTXBRK_0 Next frame transmitted is not a break 0 UCTXBRK_1 Next frame transmitted is a break or a break/synch 1 UCAxCTLW1 CTLW1 eUSCI_Ax Control Word Register 1 0x2 16 read-write n 0x3 0xFFFF UCGLIT Deglitch time 0 2 read-write UCGLIT_0 Approximately 2 ns (equivalent of 1 delay element) 0 UCGLIT_1 Approximately 50 ns 1 UCGLIT_2 Approximately 100 ns 2 UCGLIT_3 Approximately 200 ns 3 UCAxIE IE eUSCI_Ax Interrupt Enable Register 0x1A 16 read-write n 0x0 0xFFFF UCRXIE Receive interrupt enable 0 1 read-write UCRXIE_0 Interrupt disabled 0 UCRXIE_1 Interrupt enabled 1 UCSTTIE Start bit interrupt enable 2 1 read-write UCSTTIE_0 Interrupt disabled 0 UCSTTIE_1 Interrupt enabled 1 UCTXCPTIE Transmit complete interrupt enable 3 1 read-write UCTXCPTIE_0 Interrupt disabled 0 UCTXCPTIE_1 Interrupt enabled 1 UCTXIE Transmit interrupt enable 1 1 read-write UCTXIE_0 Interrupt disabled 0 UCTXIE_1 Interrupt enabled 1 UCAxIFG IFG eUSCI_Ax Interrupt Flag Register 0x1C 16 read-write n 0x2 0xFFFF UCRXIFG Receive interrupt flag 0 1 read-write UCRXIFG_0 No interrupt pending 0 UCRXIFG_1 Interrupt pending 1 UCSTTIFG Start bit interrupt flag 2 1 read-write UCSTTIFG_0 No interrupt pending 0 UCSTTIFG_1 Interrupt pending 1 UCTXCPTIFG Transmit ready interrupt enable 3 1 read-write UCTXCPTIFG_0 No interrupt pending 0 UCTXCPTIFG_1 Interrupt pending 1 UCTXIFG Transmit interrupt flag 1 1 read-write UCTXIFG_0 No interrupt pending 0 UCTXIFG_1 Interrupt pending 1 UCAxIRCTL IRCTL eUSCI_Ax IrDA Control Word Register 0x12 16 read-write n 0x0 0xFFFF UCIREN IrDA encoder/decoder enable 0 1 read-write UCIREN_0 IrDA encoder/decoder disabled 0 UCIREN_1 IrDA encoder/decoder enabled 1 UCIRRXFE IrDA receive filter enabled 8 1 read-write UCIRRXFE_0 Receive filter disabled 0 UCIRRXFE_1 Receive filter enabled 1 UCIRRXFL Receive filter length 10 4 read-write UCIRRXPL IrDA receive input UCAxRXD polarity 9 1 read-write UCIRRXPL_0 IrDA transceiver delivers a high pulse when a light pulse is seen 0 UCIRRXPL_1 IrDA transceiver delivers a low pulse when a light pulse is seen 1 UCIRTXCLK IrDA transmit pulse clock select 1 1 read-write UCIRTXCLK_0 BRCLK 0 UCIRTXCLK_1 BITCLK16 when UCOS16 = 1. Otherwise, BRCLK. 1 UCIRTXPL Transmit pulse length 2 6 read-write UCAxIV IV eUSCI_Ax Interrupt Vector Register 0x1E 16 read-only n 0x0 0xFFFF UCIV eUSCI_A interrupt vector value 0 16 read-only UCIV_enum_read read UCIV_0 No interrupt pending 0 UCIV_2 Interrupt Source: Receive buffer full Interrupt Flag: UCRXIFG Interrupt Priority: Highest 2 UCIV_4 Interrupt Source: Transmit buffer empty Interrupt Flag: UCTXIFG 4 UCIV_6 Interrupt Source: Start bit received Interrupt Flag: UCSTTIFG 6 UCIV_8 Interrupt Source: Transmit complete Interrupt Flag: UCTXCPTIFG Interrupt Priority: Lowest 8 UCAxMCTLW MCTLW eUSCI_Ax Modulation Control Word Register 0x8 16 read-write n 0x0 0xFFFF UCBRF First modulation stage select 4 4 read-write UCBRS Second modulation stage select 8 8 read-write UCOS16 Oversampling mode enabled 0 1 read-write UCOS16_0 Disabled 0 UCOS16_1 Enabled 1 UCAxRXBUF RXBUF eUSCI_Ax Receive Buffer Register 0xC 16 read-only n 0x0 0xFFFF UCRXBUF Receive data buffer 0 8 read-only UCAxSTATW STATW eUSCI_Ax Status Register 0xA 16 read-write n 0x0 0xFFFF UCADDR_UCIDLE Address received / Idle line detected 1 1 read-write UCBRK Break detect flag 3 1 read-write UCBRK_0 No break condition 0 UCBRK_1 Break condition occurred 1 UCBUSY eUSCI_A busy 0 1 read-only UCBUSY_enum_read read UCBUSY_0 eUSCI_A inactive 0 UCBUSY_1 eUSCI_A transmitting or receiving 1 UCFE Framing error flag 6 1 read-write UCFE_0 No error 0 UCFE_1 Character received with low stop bit 1 UCLISTEN Listen enable 7 1 read-write UCLISTEN_0 Disabled 0 UCLISTEN_1 Enabled. UCAxTXD is internally fed back to the receiver 1 UCOE Overrun error flag 5 1 read-write UCOE_0 No error 0 UCOE_1 Overrun error occurred 1 UCPE Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read. 4 1 read-write UCPE_0 No error 0 UCPE_1 Character received with parity error 1 UCRXERR Receive error flag 2 1 read-write UCRXERR_0 No receive errors detected 0 UCRXERR_1 Receive error detected 1 UCAxTXBUF TXBUF eUSCI_Ax Transmit Buffer Register 0xE 16 read-write n 0x0 0xFFFF UCTXBUF Transmit data buffer 0 8 read-write EUSCI_A2 EUSCI_A2 EUSCI_A2 0x40001800 0x0 0x20 registers n EUSCIA2_IRQ EUSCIA2 Interrupt 18 UCAxABCTL ABCTL eUSCI_Ax Auto Baud Rate Control Register 0x10 16 read-write n 0x0 0xFFFF UCABDEN Automatic baud-rate detect enable 0 1 read-write UCABDEN_0 Baud-rate detection disabled. Length of break and synch field is not measured. 0 UCABDEN_1 Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly. 1 UCBTOE Break time out error 2 1 read-write UCBTOE_0 No error 0 UCBTOE_1 Length of break field exceeded 22 bit times 1 UCDELIM Break/synch delimiter length 4 2 read-write UCDELIM_0 1 bit time 0 UCDELIM_1 2 bit times 1 UCDELIM_2 3 bit times 2 UCDELIM_3 4 bit times 3 UCSTOE Synch field time out error 3 1 read-write UCSTOE_0 No error 0 UCSTOE_1 Length of synch field exceeded measurable time 1 UCAxBRW BRW eUSCI_Ax Baud Rate Control Word Register 0x6 16 read-write n 0x0 0xFF UCBR Clock prescaler setting of the Baud rate generator 0 16 read-write UCAxCTLW0 CTLW0 eUSCI_Ax Control Word Register 0 0x0 16 read-write n 0x1 0xFFFF UC7BIT Character length 12 1 read-write UC7BIT_0 8-bit data 0 UC7BIT_1 7-bit data 1 UCBRKIE Receive break character interrupt enable 4 1 read-write UCBRKIE_0 Received break characters do not set UCRXIFG 0 UCBRKIE_1 Received break characters set UCRXIFG 1 UCDORM Dormant 3 1 read-write UCDORM_0 Not dormant. All received characters set UCRXIFG. 0 UCDORM_1 Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG. 1 UCMODE eUSCI_A mode 9 2 read-write UCMODE_0 UART mode 0 UCMODE_1 Idle-line multiprocessor mode 1 UCMODE_2 Address-bit multiprocessor mode 2 UCMODE_3 UART mode with automatic baud-rate detection 3 UCMSB MSB first select 13 1 read-write UCMSB_0 LSB first 0 UCMSB_1 MSB first 1 UCPAR Parity select 14 1 read-write UCPAR_0 Odd parity 0 UCPAR_1 Even parity 1 UCPEN Parity enable 15 1 read-write UCPEN_0 Parity disabled 0 UCPEN_1 Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation. 1 UCRXEIE Receive erroneous-character interrupt enable 5 1 read-write UCRXEIE_0 Erroneous characters rejected and UCRXIFG is not set 0 UCRXEIE_1 Erroneous characters received set UCRXIFG 1 UCSPB Stop bit select 11 1 read-write UCSPB_0 One stop bit 0 UCSPB_1 Two stop bits 1 UCSSEL eUSCI_A clock source select 6 2 read-write UCSSEL_0 UCLK 0 UCSSEL_1 ACLK 1 UCSSEL_2 SMCLK 2 UCSWRST Software reset enable 0 1 read-write UCSWRST_0 Disabled. eUSCI_A reset released for operation 0 UCSWRST_1 Enabled. eUSCI_A logic held in reset state 1 UCSYNC Synchronous mode enable 8 1 read-write UCSYNC_0 Asynchronous mode 0 UCSYNC_1 Synchronous mode 1 UCTXADDR Transmit address 2 1 read-write UCTXADDR_0 Next frame transmitted is data 0 UCTXADDR_1 Next frame transmitted is an address 1 UCTXBRK Transmit break 1 1 read-write UCTXBRK_0 Next frame transmitted is not a break 0 UCTXBRK_1 Next frame transmitted is a break or a break/synch 1 UCAxCTLW1 CTLW1 eUSCI_Ax Control Word Register 1 0x2 16 read-write n 0x3 0xFFFF UCGLIT Deglitch time 0 2 read-write UCGLIT_0 Approximately 2 ns (equivalent of 1 delay element) 0 UCGLIT_1 Approximately 50 ns 1 UCGLIT_2 Approximately 100 ns 2 UCGLIT_3 Approximately 200 ns 3 UCAxIE IE eUSCI_Ax Interrupt Enable Register 0x1A 16 read-write n 0x0 0xFFFF UCRXIE Receive interrupt enable 0 1 read-write UCRXIE_0 Interrupt disabled 0 UCRXIE_1 Interrupt enabled 1 UCSTTIE Start bit interrupt enable 2 1 read-write UCSTTIE_0 Interrupt disabled 0 UCSTTIE_1 Interrupt enabled 1 UCTXCPTIE Transmit complete interrupt enable 3 1 read-write UCTXCPTIE_0 Interrupt disabled 0 UCTXCPTIE_1 Interrupt enabled 1 UCTXIE Transmit interrupt enable 1 1 read-write UCTXIE_0 Interrupt disabled 0 UCTXIE_1 Interrupt enabled 1 UCAxIFG IFG eUSCI_Ax Interrupt Flag Register 0x1C 16 read-write n 0x2 0xFFFF UCRXIFG Receive interrupt flag 0 1 read-write UCRXIFG_0 No interrupt pending 0 UCRXIFG_1 Interrupt pending 1 UCSTTIFG Start bit interrupt flag 2 1 read-write UCSTTIFG_0 No interrupt pending 0 UCSTTIFG_1 Interrupt pending 1 UCTXCPTIFG Transmit ready interrupt enable 3 1 read-write UCTXCPTIFG_0 No interrupt pending 0 UCTXCPTIFG_1 Interrupt pending 1 UCTXIFG Transmit interrupt flag 1 1 read-write UCTXIFG_0 No interrupt pending 0 UCTXIFG_1 Interrupt pending 1 UCAxIRCTL IRCTL eUSCI_Ax IrDA Control Word Register 0x12 16 read-write n 0x0 0xFFFF UCIREN IrDA encoder/decoder enable 0 1 read-write UCIREN_0 IrDA encoder/decoder disabled 0 UCIREN_1 IrDA encoder/decoder enabled 1 UCIRRXFE IrDA receive filter enabled 8 1 read-write UCIRRXFE_0 Receive filter disabled 0 UCIRRXFE_1 Receive filter enabled 1 UCIRRXFL Receive filter length 10 4 read-write UCIRRXPL IrDA receive input UCAxRXD polarity 9 1 read-write UCIRRXPL_0 IrDA transceiver delivers a high pulse when a light pulse is seen 0 UCIRRXPL_1 IrDA transceiver delivers a low pulse when a light pulse is seen 1 UCIRTXCLK IrDA transmit pulse clock select 1 1 read-write UCIRTXCLK_0 BRCLK 0 UCIRTXCLK_1 BITCLK16 when UCOS16 = 1. Otherwise, BRCLK. 1 UCIRTXPL Transmit pulse length 2 6 read-write UCAxIV IV eUSCI_Ax Interrupt Vector Register 0x1E 16 read-only n 0x0 0xFFFF UCIV eUSCI_A interrupt vector value 0 16 read-only UCIV_enum_read read UCIV_0 No interrupt pending 0 UCIV_2 Interrupt Source: Receive buffer full Interrupt Flag: UCRXIFG Interrupt Priority: Highest 2 UCIV_4 Interrupt Source: Transmit buffer empty Interrupt Flag: UCTXIFG 4 UCIV_6 Interrupt Source: Start bit received Interrupt Flag: UCSTTIFG 6 UCIV_8 Interrupt Source: Transmit complete Interrupt Flag: UCTXCPTIFG Interrupt Priority: Lowest 8 UCAxMCTLW MCTLW eUSCI_Ax Modulation Control Word Register 0x8 16 read-write n 0x0 0xFFFF UCBRF First modulation stage select 4 4 read-write UCBRS Second modulation stage select 8 8 read-write UCOS16 Oversampling mode enabled 0 1 read-write UCOS16_0 Disabled 0 UCOS16_1 Enabled 1 UCAxRXBUF RXBUF eUSCI_Ax Receive Buffer Register 0xC 16 read-only n 0x0 0xFFFF UCRXBUF Receive data buffer 0 8 read-only UCAxSTATW STATW eUSCI_Ax Status Register 0xA 16 read-write n 0x0 0xFFFF UCADDR_UCIDLE Address received / Idle line detected 1 1 read-write UCBRK Break detect flag 3 1 read-write UCBRK_0 No break condition 0 UCBRK_1 Break condition occurred 1 UCBUSY eUSCI_A busy 0 1 read-only UCBUSY_enum_read read UCBUSY_0 eUSCI_A inactive 0 UCBUSY_1 eUSCI_A transmitting or receiving 1 UCFE Framing error flag 6 1 read-write UCFE_0 No error 0 UCFE_1 Character received with low stop bit 1 UCLISTEN Listen enable 7 1 read-write UCLISTEN_0 Disabled 0 UCLISTEN_1 Enabled. UCAxTXD is internally fed back to the receiver 1 UCOE Overrun error flag 5 1 read-write UCOE_0 No error 0 UCOE_1 Overrun error occurred 1 UCPE Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read. 4 1 read-write UCPE_0 No error 0 UCPE_1 Character received with parity error 1 UCRXERR Receive error flag 2 1 read-write UCRXERR_0 No receive errors detected 0 UCRXERR_1 Receive error detected 1 UCAxTXBUF TXBUF eUSCI_Ax Transmit Buffer Register 0xE 16 read-write n 0x0 0xFFFF UCTXBUF Transmit data buffer 0 8 read-write EUSCI_B0 EUSCI_B0 EUSCI_B0 0x40002000 0x0 0x30 registers n EUSCIB0_IRQ EUSCIB0 Interrupt 20 UCBxADDMASK ADDMASK eUSCI_Bx I2C Address Mask Register 0x1E 16 read-write n 0x3FF 0xFFFF ADDMASK Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated. Modify only when UCSWRST = 1. 0 10 read-write UCBxADDRX ADDRX eUSCI_Bx I2C Received Address Register 0x1C 16 read-only n 0x0 0xFFFF ADDRX Received Address Register 0 10 read-only UCBxBRW BRW eUSCI_Bx Baud Rate Control Word Register 0x6 16 read-write n 0x0 0xFFFF UCBR Bit clock prescaler 0 16 read-write UCBxCTLW0 CTLW0 eUSCI_Bx Control Word Register 0 0x0 16 read-write n 0x1C1 0xFFFF UCA10 Own addressing mode select 15 1 read-write UCA10_0 Own address is a 7-bit address 0 UCA10_1 Own address is a 10-bit address 1 UCMM Multi-master environment select 13 1 read-write UCMM_0 Single master environment. There is no other master in the system. The address compare unit is disabled. 0 UCMM_1 Multi-master environment 1 UCMODE eUSCI_B mode 9 2 read-write UCMODE_0 3-pin SPI 0 UCMODE_1 4-pin SPI (master or slave enabled if STE = 1) 1 UCMODE_2 4-pin SPI (master or slave enabled if STE = 0) 2 UCMODE_3 I2C mode 3 UCMST Master mode select 11 1 read-write UCMST_0 Slave mode 0 UCMST_1 Master mode 1 UCSLA10 Slave addressing mode select 14 1 read-write UCSLA10_0 Address slave with 7-bit address 0 UCSLA10_1 Address slave with 10-bit address 1 UCSSEL eUSCI_B clock source select 6 2 read-write UCSSEL_0 UCLKI 0 UCSSEL_1 ACLK 1 UCSSEL_2 SMCLK 2 UCSSEL_3 SMCLK 3 UCSWRST Software reset enable 0 1 read-write UCSWRST_0 Disabled. eUSCI_B reset released for operation 0 UCSWRST_1 Enabled. eUSCI_B logic held in reset state 1 UCSYNC Synchronous mode enable 8 1 read-write UCSYNC_0 Asynchronous mode 0 UCSYNC_1 Synchronous mode 1 UCTR Transmitter/receiver 4 1 read-write UCTR_0 Receiver 0 UCTR_1 Transmitter 1 UCTXACK Transmit ACK condition in slave mode 5 1 read-write UCTXACK_0 Do not acknowledge the slave address 0 UCTXACK_1 Acknowledge the slave address 1 UCTXNACK Transmit a NACK 3 1 read-write UCTXNACK_0 Acknowledge normally 0 UCTXNACK_1 Generate NACK 1 UCTXSTP Transmit STOP condition in master mode 2 1 read-write UCTXSTP_0 No STOP generated 0 UCTXSTP_1 Generate STOP 1 UCTXSTT Transmit START condition in master mode 1 1 read-write UCTXSTT_0 Do not generate START condition 0 UCTXSTT_1 Generate START condition 1 UCBxCTLW1 CTLW1 eUSCI_Bx Control Word Register 1 0x2 16 read-write n 0x3 0xFFFF UCASTP Automatic STOP condition generation 2 2 read-write UCASTP_0 No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. 0 UCASTP_1 UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT 1 UCASTP_2 A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold 2 UCCLTO Clock low timeout select 6 2 read-write UCCLTO_0 Disable clock low timeout counter 0 UCCLTO_1 135 000 SYSCLK cycles (approximately 28 ms) 1 UCCLTO_2 150 000 SYSCLK cycles (approximately 31 ms) 2 UCCLTO_3 165 000 SYSCLK cycles (approximately 34 ms) 3 UCETXINT Early UCTXIFG0 8 1 read-write UCETXINT_0 UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit 0 UCETXINT_1 UCTXIFG0 is set for each START condition 1 UCGLIT Deglitch time 0 2 read-write UCGLIT_0 50 ns 0 UCGLIT_1 25 ns 1 UCGLIT_2 12.5 ns 2 UCGLIT_3 6.25 ns 3 UCSTPNACK ACK all master bytes 5 1 read-write UCSTPNACK_0 Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard) 0 UCSTPNACK_1 All bytes are acknowledged by the eUSCI_B when configured as master receiver 1 UCSWACK SW or HW ACK control 4 1 read-write UCSWACK_0 The address acknowledge of the slave is controlled by the eUSCI_B module 0 UCSWACK_1 The user needs to trigger the sending of the address ACK by issuing UCTXACK 1 UCBxI2COA0 I2COA0 eUSCI_Bx I2C Own Address 0 Register 0x14 16 read-write n 0x0 0xFFFF I2COA0 I2C own address 0 10 read-write UCGCEN General call response enable 15 1 read-write UCGCEN_0 Do not respond to a general call 0 UCGCEN_1 Respond to a general call 1 UCOAEN Own Address enable register 10 1 read-write UCOAEN_0 The slave address defined in I2COA0 is disabled 0 UCOAEN_1 The slave address defined in I2COA0 is enabled 1 UCBxI2COA1 I2COA1 eUSCI_Bx I2C Own Address 1 Register 0x16 16 read-write n 0x0 0xFFFF I2COA1 I2C own address 0 10 read-write UCOAEN Own Address enable register 10 1 read-write UCOAEN_0 The slave address defined in I2COA1 is disabled 0 UCOAEN_1 The slave address defined in I2COA1 is enabled 1 UCBxI2COA2 I2COA2 eUSCI_Bx I2C Own Address 2 Register 0x18 16 read-write n 0x0 0xFFFF I2COA2 I2C own address 0 10 read-write UCOAEN Own Address enable register 10 1 read-write UCOAEN_0 The slave address defined in I2COA2 is disabled 0 UCOAEN_1 The slave address defined in I2COA2 is enabled 1 UCBxI2COA3 I2COA3 eUSCI_Bx I2C Own Address 3 Register 0x1A 16 read-write n 0x0 0xFFFF I2COA3 I2C own address 0 10 read-write UCOAEN Own Address enable register 10 1 read-write UCOAEN_0 The slave address defined in I2COA3 is disabled 0 UCOAEN_1 The slave address defined in I2COA3 is enabled 1 UCBxI2CSA I2CSA eUSCI_Bx I2C Slave Address Register 0x20 16 read-write n 0x0 0xFFFF I2CSA I2C slave address 0 10 read-write UCBxIE IE eUSCI_Bx Interrupt Enable Register 0x2A 16 read-write n 0x0 0xFFFF UCALIE Arbitration lost interrupt enable 4 1 read-write UCALIE_0 Interrupt disabled 0 UCALIE_1 Interrupt enabled 1 UCBCNTIE Byte counter interrupt enable 6 1 read-write UCBCNTIE_0 Interrupt disabled 0 UCBCNTIE_1 Interrupt enabled 1 UCBIT9IE Bit position 9 interrupt enable 14 1 read-write UCBIT9IE_0 Interrupt disabled 0 UCBIT9IE_1 Interrupt enabled 1 UCCLTOIE Clock low timeout interrupt enable 7 1 read-write UCCLTOIE_0 Interrupt disabled 0 UCCLTOIE_1 Interrupt enabled 1 UCNACKIE Not-acknowledge interrupt enable 5 1 read-write UCNACKIE_0 Interrupt disabled 0 UCNACKIE_1 Interrupt enabled 1 UCRXIE0 Receive interrupt enable 0 0 1 read-write UCRXIE0_0 Interrupt disabled 0 UCRXIE0_1 Interrupt enabled 1 UCRXIE1 Receive interrupt enable 1 8 1 read-write UCRXIE1_0 Interrupt disabled 0 UCRXIE1_1 Interrupt enabled 1 UCRXIE2 Receive interrupt enable 2 10 1 read-write UCRXIE2_0 Interrupt disabled 0 UCRXIE2_1 Interrupt enabled 1 UCRXIE3 Receive interrupt enable 3 12 1 read-write UCRXIE3_0 Interrupt disabled 0 UCRXIE3_1 Interrupt enabled 1 UCSTPIE STOP condition interrupt enable 3 1 read-write UCSTPIE_0 Interrupt disabled 0 UCSTPIE_1 Interrupt enabled 1 UCSTTIE START condition interrupt enable 2 1 read-write UCSTTIE_0 Interrupt disabled 0 UCSTTIE_1 Interrupt enabled 1 UCTXIE0 Transmit interrupt enable 0 1 1 read-write UCTXIE0_0 Interrupt disabled 0 UCTXIE0_1 Interrupt enabled 1 UCTXIE1 Transmit interrupt enable 1 9 1 read-write UCTXIE1_0 Interrupt disabled 0 UCTXIE1_1 Interrupt enabled 1 UCTXIE2 Transmit interrupt enable 2 11 1 read-write UCTXIE2_0 Interrupt disabled 0 UCTXIE2_1 Interrupt enabled 1 UCTXIE3 Transmit interrupt enable 3 13 1 read-write UCTXIE3_0 Interrupt disabled 0 UCTXIE3_1 Interrupt enabled 1 UCBxIFG IFG eUSCI_Bx Interrupt Flag Register 0x2C 16 read-write n 0x2 0xFFFF UCALIFG Arbitration lost interrupt flag 4 1 read-write UCALIFG_0 No interrupt pending 0 UCALIFG_1 Interrupt pending 1 UCBCNTIFG Byte counter interrupt flag 6 1 read-write UCBCNTIFG_0 No interrupt pending 0 UCBCNTIFG_1 Interrupt pending 1 UCBIT9IFG Bit position 9 interrupt flag 14 1 read-write UCBIT9IFG_0 No interrupt pending 0 UCBIT9IFG_1 Interrupt pending 1 UCCLTOIFG Clock low timeout interrupt flag 7 1 read-write UCCLTOIFG_0 No interrupt pending 0 UCCLTOIFG_1 Interrupt pending 1 UCNACKIFG Not-acknowledge received interrupt flag 5 1 read-write UCNACKIFG_0 No interrupt pending 0 UCNACKIFG_1 Interrupt pending 1 UCRXIFG0 eUSCI_B receive interrupt flag 0 0 1 read-write UCRXIFG0_0 No interrupt pending 0 UCRXIFG0_1 Interrupt pending 1 UCRXIFG1 eUSCI_B receive interrupt flag 1 8 1 read-write UCRXIFG1_0 No interrupt pending 0 UCRXIFG1_1 Interrupt pending 1 UCRXIFG2 eUSCI_B receive interrupt flag 2 10 1 read-write UCRXIFG2_0 No interrupt pending 0 UCRXIFG2_1 Interrupt pending 1 UCRXIFG3 eUSCI_B receive interrupt flag 3 12 1 read-write UCRXIFG3_0 No interrupt pending 0 UCRXIFG3_1 Interrupt pending 1 UCSTPIFG STOP condition interrupt flag 3 1 read-write UCSTPIFG_0 No interrupt pending 0 UCSTPIFG_1 Interrupt pending 1 UCSTTIFG START condition interrupt flag 2 1 read-write UCSTTIFG_0 No interrupt pending 0 UCSTTIFG_1 Interrupt pending 1 UCTXIFG0 eUSCI_B transmit interrupt flag 0 1 1 read-write UCTXIFG0_0 No interrupt pending 0 UCTXIFG0_1 Interrupt pending 1 UCTXIFG1 eUSCI_B transmit interrupt flag 1 9 1 read-write UCTXIFG1_0 No interrupt pending 0 UCTXIFG1_1 Interrupt pending 1 UCTXIFG2 eUSCI_B transmit interrupt flag 2 11 1 read-write UCTXIFG2_0 No interrupt pending 0 UCTXIFG2_1 Interrupt pending 1 UCTXIFG3 eUSCI_B transmit interrupt flag 3 13 1 read-write UCTXIFG3_0 No interrupt pending 0 UCTXIFG3_1 Interrupt pending 1 UCBxIV IV eUSCI_Bx Interrupt Vector Register 0x2E 16 read-only n 0x0 0xFFFF UCIV eUSCI_B interrupt vector value 0 16 read-only UCIV_enum_read read UCIV_0 No interrupt pending 0 UCIV_10 Interrupt Source: Slave 3 Data received Interrupt Flag: UCRXIFG3 10 UCIV_12 Interrupt Source: Slave 3 Transmit buffer empty Interrupt Flag: UCTXIFG3 12 UCIV_14 Interrupt Source: Slave 2 Data received Interrupt Flag: UCRXIFG2 14 UCIV_16 Interrupt Source: Slave 2 Transmit buffer empty Interrupt Flag: UCTXIFG2 16 UCIV_18 Interrupt Source: Slave 1 Data received Interrupt Flag: UCRXIFG1 18 UCIV_2 Interrupt Source: Arbitration lost Interrupt Flag: UCALIFG Interrupt Priority: Highest 2 UCIV_20 Interrupt Source: Slave 1 Transmit buffer empty Interrupt Flag: UCTXIFG1 20 UCIV_22 Interrupt Source: Data received Interrupt Flag: UCRXIFG0 22 UCIV_24 Interrupt Source: Transmit buffer empty Interrupt Flag: UCTXIFG0 24 UCIV_26 Interrupt Source: Byte counter zero Interrupt Flag: UCBCNTIFG 26 UCIV_28 Interrupt Source: Clock low timeout Interrupt Flag: UCCLTOIFG 28 UCIV_30 Interrupt Source: Nineth bit position Interrupt Flag: UCBIT9IFG Priority: Lowest 30 UCIV_4 Interrupt Source: Not acknowledgment Interrupt Flag: UCNACKIFG 4 UCIV_6 Interrupt Source: Start condition received Interrupt Flag: UCSTTIFG 6 UCIV_8 Interrupt Source: Stop condition received Interrupt Flag: UCSTPIFG 8 UCBxRXBUF RXBUF eUSCI_Bx Receive Buffer Register 0xC 16 read-only n 0x0 0xFFFF UCRXBUF Receive data buffer 0 8 read-only UCBxSTATW STATW eUSCI_Bx Status Register 0x8 16 read-write n 0x0 0xFFFF UCBBUSY Bus busy 4 1 read-only UCBBUSY_enum_read read UCBBUSY_0 Bus inactive 0 UCBBUSY_1 Bus busy 1 UCBCNT Hardware byte counter value 8 8 read-only UCGC General call address received 5 1 read-only UCGC_enum_read read UCGC_0 No general call address received 0 UCGC_1 General call address received 1 UCSCLLOW SCL low 6 1 read-only UCSCLLOW_enum_read read UCSCLLOW_0 SCL is not held low 0 UCSCLLOW_1 SCL is held low 1 UCBxTBCNT TBCNT eUSCI_Bx Byte Counter Threshold Register 0xA 16 read-write n 0x0 0xFFFF UCTBCNT Byte counter threshold value 0 8 read-write UCBxTXBUF TXBUF eUSCI_Bx Transmit Buffer Register 0xE 16 read-write n 0x0 0xFFFF UCTXBUF Transmit data buffer 0 8 read-write EUSCI_B2 EUSCI_B2 EUSCI_B2 0x40002800 0x0 0x30 registers n EUSCIB2_IRQ EUSCIB2 Interrupt 22 UCBxADDMASK ADDMASK eUSCI_Bx I2C Address Mask Register 0x1E 16 read-write n 0x3FF 0xFFFF ADDMASK Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated. Modify only when UCSWRST = 1. 0 10 read-write UCBxADDRX ADDRX eUSCI_Bx I2C Received Address Register 0x1C 16 read-only n 0x0 0xFFFF ADDRX Received Address Register 0 10 read-only UCBxBRW BRW eUSCI_Bx Baud Rate Control Word Register 0x6 16 read-write n 0x0 0xFFFF UCBR Bit clock prescaler 0 16 read-write UCBxCTLW0 CTLW0 eUSCI_Bx Control Word Register 0 0x0 16 read-write n 0x1C1 0xFFFF UCA10 Own addressing mode select 15 1 read-write UCA10_0 Own address is a 7-bit address 0 UCA10_1 Own address is a 10-bit address 1 UCMM Multi-master environment select 13 1 read-write UCMM_0 Single master environment. There is no other master in the system. The address compare unit is disabled. 0 UCMM_1 Multi-master environment 1 UCMODE eUSCI_B mode 9 2 read-write UCMODE_0 3-pin SPI 0 UCMODE_1 4-pin SPI (master or slave enabled if STE = 1) 1 UCMODE_2 4-pin SPI (master or slave enabled if STE = 0) 2 UCMODE_3 I2C mode 3 UCMST Master mode select 11 1 read-write UCMST_0 Slave mode 0 UCMST_1 Master mode 1 UCSLA10 Slave addressing mode select 14 1 read-write UCSLA10_0 Address slave with 7-bit address 0 UCSLA10_1 Address slave with 10-bit address 1 UCSSEL eUSCI_B clock source select 6 2 read-write UCSSEL_0 UCLKI 0 UCSSEL_1 ACLK 1 UCSSEL_2 SMCLK 2 UCSSEL_3 SMCLK 3 UCSWRST Software reset enable 0 1 read-write UCSWRST_0 Disabled. eUSCI_B reset released for operation 0 UCSWRST_1 Enabled. eUSCI_B logic held in reset state 1 UCSYNC Synchronous mode enable 8 1 read-write UCSYNC_0 Asynchronous mode 0 UCSYNC_1 Synchronous mode 1 UCTR Transmitter/receiver 4 1 read-write UCTR_0 Receiver 0 UCTR_1 Transmitter 1 UCTXACK Transmit ACK condition in slave mode 5 1 read-write UCTXACK_0 Do not acknowledge the slave address 0 UCTXACK_1 Acknowledge the slave address 1 UCTXNACK Transmit a NACK 3 1 read-write UCTXNACK_0 Acknowledge normally 0 UCTXNACK_1 Generate NACK 1 UCTXSTP Transmit STOP condition in master mode 2 1 read-write UCTXSTP_0 No STOP generated 0 UCTXSTP_1 Generate STOP 1 UCTXSTT Transmit START condition in master mode 1 1 read-write UCTXSTT_0 Do not generate START condition 0 UCTXSTT_1 Generate START condition 1 UCBxCTLW1 CTLW1 eUSCI_Bx Control Word Register 1 0x2 16 read-write n 0x3 0xFFFF UCASTP Automatic STOP condition generation 2 2 read-write UCASTP_0 No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. 0 UCASTP_1 UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT 1 UCASTP_2 A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold 2 UCCLTO Clock low timeout select 6 2 read-write UCCLTO_0 Disable clock low timeout counter 0 UCCLTO_1 135 000 SYSCLK cycles (approximately 28 ms) 1 UCCLTO_2 150 000 SYSCLK cycles (approximately 31 ms) 2 UCCLTO_3 165 000 SYSCLK cycles (approximately 34 ms) 3 UCETXINT Early UCTXIFG0 8 1 read-write UCETXINT_0 UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit 0 UCETXINT_1 UCTXIFG0 is set for each START condition 1 UCGLIT Deglitch time 0 2 read-write UCGLIT_0 50 ns 0 UCGLIT_1 25 ns 1 UCGLIT_2 12.5 ns 2 UCGLIT_3 6.25 ns 3 UCSTPNACK ACK all master bytes 5 1 read-write UCSTPNACK_0 Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard) 0 UCSTPNACK_1 All bytes are acknowledged by the eUSCI_B when configured as master receiver 1 UCSWACK SW or HW ACK control 4 1 read-write UCSWACK_0 The address acknowledge of the slave is controlled by the eUSCI_B module 0 UCSWACK_1 The user needs to trigger the sending of the address ACK by issuing UCTXACK 1 UCBxI2COA0 I2COA0 eUSCI_Bx I2C Own Address 0 Register 0x14 16 read-write n 0x0 0xFFFF I2COA0 I2C own address 0 10 read-write UCGCEN General call response enable 15 1 read-write UCGCEN_0 Do not respond to a general call 0 UCGCEN_1 Respond to a general call 1 UCOAEN Own Address enable register 10 1 read-write UCOAEN_0 The slave address defined in I2COA0 is disabled 0 UCOAEN_1 The slave address defined in I2COA0 is enabled 1 UCBxI2COA1 I2COA1 eUSCI_Bx I2C Own Address 1 Register 0x16 16 read-write n 0x0 0xFFFF I2COA1 I2C own address 0 10 read-write UCOAEN Own Address enable register 10 1 read-write UCOAEN_0 The slave address defined in I2COA1 is disabled 0 UCOAEN_1 The slave address defined in I2COA1 is enabled 1 UCBxI2COA2 I2COA2 eUSCI_Bx I2C Own Address 2 Register 0x18 16 read-write n 0x0 0xFFFF I2COA2 I2C own address 0 10 read-write UCOAEN Own Address enable register 10 1 read-write UCOAEN_0 The slave address defined in I2COA2 is disabled 0 UCOAEN_1 The slave address defined in I2COA2 is enabled 1 UCBxI2COA3 I2COA3 eUSCI_Bx I2C Own Address 3 Register 0x1A 16 read-write n 0x0 0xFFFF I2COA3 I2C own address 0 10 read-write UCOAEN Own Address enable register 10 1 read-write UCOAEN_0 The slave address defined in I2COA3 is disabled 0 UCOAEN_1 The slave address defined in I2COA3 is enabled 1 UCBxI2CSA I2CSA eUSCI_Bx I2C Slave Address Register 0x20 16 read-write n 0x0 0xFFFF I2CSA I2C slave address 0 10 read-write UCBxIE IE eUSCI_Bx Interrupt Enable Register 0x2A 16 read-write n 0x0 0xFFFF UCALIE Arbitration lost interrupt enable 4 1 read-write UCALIE_0 Interrupt disabled 0 UCALIE_1 Interrupt enabled 1 UCBCNTIE Byte counter interrupt enable 6 1 read-write UCBCNTIE_0 Interrupt disabled 0 UCBCNTIE_1 Interrupt enabled 1 UCBIT9IE Bit position 9 interrupt enable 14 1 read-write UCBIT9IE_0 Interrupt disabled 0 UCBIT9IE_1 Interrupt enabled 1 UCCLTOIE Clock low timeout interrupt enable 7 1 read-write UCCLTOIE_0 Interrupt disabled 0 UCCLTOIE_1 Interrupt enabled 1 UCNACKIE Not-acknowledge interrupt enable 5 1 read-write UCNACKIE_0 Interrupt disabled 0 UCNACKIE_1 Interrupt enabled 1 UCRXIE0 Receive interrupt enable 0 0 1 read-write UCRXIE0_0 Interrupt disabled 0 UCRXIE0_1 Interrupt enabled 1 UCRXIE1 Receive interrupt enable 1 8 1 read-write UCRXIE1_0 Interrupt disabled 0 UCRXIE1_1 Interrupt enabled 1 UCRXIE2 Receive interrupt enable 2 10 1 read-write UCRXIE2_0 Interrupt disabled 0 UCRXIE2_1 Interrupt enabled 1 UCRXIE3 Receive interrupt enable 3 12 1 read-write UCRXIE3_0 Interrupt disabled 0 UCRXIE3_1 Interrupt enabled 1 UCSTPIE STOP condition interrupt enable 3 1 read-write UCSTPIE_0 Interrupt disabled 0 UCSTPIE_1 Interrupt enabled 1 UCSTTIE START condition interrupt enable 2 1 read-write UCSTTIE_0 Interrupt disabled 0 UCSTTIE_1 Interrupt enabled 1 UCTXIE0 Transmit interrupt enable 0 1 1 read-write UCTXIE0_0 Interrupt disabled 0 UCTXIE0_1 Interrupt enabled 1 UCTXIE1 Transmit interrupt enable 1 9 1 read-write UCTXIE1_0 Interrupt disabled 0 UCTXIE1_1 Interrupt enabled 1 UCTXIE2 Transmit interrupt enable 2 11 1 read-write UCTXIE2_0 Interrupt disabled 0 UCTXIE2_1 Interrupt enabled 1 UCTXIE3 Transmit interrupt enable 3 13 1 read-write UCTXIE3_0 Interrupt disabled 0 UCTXIE3_1 Interrupt enabled 1 UCBxIFG IFG eUSCI_Bx Interrupt Flag Register 0x2C 16 read-write n 0x2 0xFFFF UCALIFG Arbitration lost interrupt flag 4 1 read-write UCALIFG_0 No interrupt pending 0 UCALIFG_1 Interrupt pending 1 UCBCNTIFG Byte counter interrupt flag 6 1 read-write UCBCNTIFG_0 No interrupt pending 0 UCBCNTIFG_1 Interrupt pending 1 UCBIT9IFG Bit position 9 interrupt flag 14 1 read-write UCBIT9IFG_0 No interrupt pending 0 UCBIT9IFG_1 Interrupt pending 1 UCCLTOIFG Clock low timeout interrupt flag 7 1 read-write UCCLTOIFG_0 No interrupt pending 0 UCCLTOIFG_1 Interrupt pending 1 UCNACKIFG Not-acknowledge received interrupt flag 5 1 read-write UCNACKIFG_0 No interrupt pending 0 UCNACKIFG_1 Interrupt pending 1 UCRXIFG0 eUSCI_B receive interrupt flag 0 0 1 read-write UCRXIFG0_0 No interrupt pending 0 UCRXIFG0_1 Interrupt pending 1 UCRXIFG1 eUSCI_B receive interrupt flag 1 8 1 read-write UCRXIFG1_0 No interrupt pending 0 UCRXIFG1_1 Interrupt pending 1 UCRXIFG2 eUSCI_B receive interrupt flag 2 10 1 read-write UCRXIFG2_0 No interrupt pending 0 UCRXIFG2_1 Interrupt pending 1 UCRXIFG3 eUSCI_B receive interrupt flag 3 12 1 read-write UCRXIFG3_0 No interrupt pending 0 UCRXIFG3_1 Interrupt pending 1 UCSTPIFG STOP condition interrupt flag 3 1 read-write UCSTPIFG_0 No interrupt pending 0 UCSTPIFG_1 Interrupt pending 1 UCSTTIFG START condition interrupt flag 2 1 read-write UCSTTIFG_0 No interrupt pending 0 UCSTTIFG_1 Interrupt pending 1 UCTXIFG0 eUSCI_B transmit interrupt flag 0 1 1 read-write UCTXIFG0_0 No interrupt pending 0 UCTXIFG0_1 Interrupt pending 1 UCTXIFG1 eUSCI_B transmit interrupt flag 1 9 1 read-write UCTXIFG1_0 No interrupt pending 0 UCTXIFG1_1 Interrupt pending 1 UCTXIFG2 eUSCI_B transmit interrupt flag 2 11 1 read-write UCTXIFG2_0 No interrupt pending 0 UCTXIFG2_1 Interrupt pending 1 UCTXIFG3 eUSCI_B transmit interrupt flag 3 13 1 read-write UCTXIFG3_0 No interrupt pending 0 UCTXIFG3_1 Interrupt pending 1 UCBxIV IV eUSCI_Bx Interrupt Vector Register 0x2E 16 read-only n 0x0 0xFFFF UCIV eUSCI_B interrupt vector value 0 16 read-only UCIV_enum_read read UCIV_0 No interrupt pending 0 UCIV_10 Interrupt Source: Slave 3 Data received Interrupt Flag: UCRXIFG3 10 UCIV_12 Interrupt Source: Slave 3 Transmit buffer empty Interrupt Flag: UCTXIFG3 12 UCIV_14 Interrupt Source: Slave 2 Data received Interrupt Flag: UCRXIFG2 14 UCIV_16 Interrupt Source: Slave 2 Transmit buffer empty Interrupt Flag: UCTXIFG2 16 UCIV_18 Interrupt Source: Slave 1 Data received Interrupt Flag: UCRXIFG1 18 UCIV_2 Interrupt Source: Arbitration lost Interrupt Flag: UCALIFG Interrupt Priority: Highest 2 UCIV_20 Interrupt Source: Slave 1 Transmit buffer empty Interrupt Flag: UCTXIFG1 20 UCIV_22 Interrupt Source: Data received Interrupt Flag: UCRXIFG0 22 UCIV_24 Interrupt Source: Transmit buffer empty Interrupt Flag: UCTXIFG0 24 UCIV_26 Interrupt Source: Byte counter zero Interrupt Flag: UCBCNTIFG 26 UCIV_28 Interrupt Source: Clock low timeout Interrupt Flag: UCCLTOIFG 28 UCIV_30 Interrupt Source: Nineth bit position Interrupt Flag: UCBIT9IFG Priority: Lowest 30 UCIV_4 Interrupt Source: Not acknowledgment Interrupt Flag: UCNACKIFG 4 UCIV_6 Interrupt Source: Start condition received Interrupt Flag: UCSTTIFG 6 UCIV_8 Interrupt Source: Stop condition received Interrupt Flag: UCSTPIFG 8 UCBxRXBUF RXBUF eUSCI_Bx Receive Buffer Register 0xC 16 read-only n 0x0 0xFFFF UCRXBUF Receive data buffer 0 8 read-only UCBxSTATW STATW eUSCI_Bx Status Register 0x8 16 read-write n 0x0 0xFFFF UCBBUSY Bus busy 4 1 read-only UCBBUSY_enum_read read UCBBUSY_0 Bus inactive 0 UCBBUSY_1 Bus busy 1 UCBCNT Hardware byte counter value 8 8 read-only UCGC General call address received 5 1 read-only UCGC_enum_read read UCGC_0 No general call address received 0 UCGC_1 General call address received 1 UCSCLLOW SCL low 6 1 read-only UCSCLLOW_enum_read read UCSCLLOW_0 SCL is not held low 0 UCSCLLOW_1 SCL is held low 1 UCBxTBCNT TBCNT eUSCI_Bx Byte Counter Threshold Register 0xA 16 read-write n 0x0 0xFFFF UCTBCNT Byte counter threshold value 0 8 read-write UCBxTXBUF TXBUF eUSCI_Bx Transmit Buffer Register 0xE 16 read-write n 0x0 0xFFFF UCTXBUF Transmit data buffer 0 8 read-write EUSCI_B3 EUSCI_B3 EUSCI_B3 0x40002C00 0x0 0x30 registers n EUSCIB3_IRQ EUSCIB3 Interrupt 23 UCBxADDMASK ADDMASK eUSCI_Bx I2C Address Mask Register 0x1E 16 read-write n 0x3FF 0xFFFF ADDMASK Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated. Modify only when UCSWRST = 1. 0 10 read-write UCBxADDRX ADDRX eUSCI_Bx I2C Received Address Register 0x1C 16 read-only n 0x0 0xFFFF ADDRX Received Address Register 0 10 read-only UCBxBRW BRW eUSCI_Bx Baud Rate Control Word Register 0x6 16 read-write n 0x0 0xFFFF UCBR Bit clock prescaler 0 16 read-write UCBxCTLW0 CTLW0 eUSCI_Bx Control Word Register 0 0x0 16 read-write n 0x1C1 0xFFFF UCA10 Own addressing mode select 15 1 read-write UCA10_0 Own address is a 7-bit address 0 UCA10_1 Own address is a 10-bit address 1 UCMM Multi-master environment select 13 1 read-write UCMM_0 Single master environment. There is no other master in the system. The address compare unit is disabled. 0 UCMM_1 Multi-master environment 1 UCMODE eUSCI_B mode 9 2 read-write UCMODE_0 3-pin SPI 0 UCMODE_1 4-pin SPI (master or slave enabled if STE = 1) 1 UCMODE_2 4-pin SPI (master or slave enabled if STE = 0) 2 UCMODE_3 I2C mode 3 UCMST Master mode select 11 1 read-write UCMST_0 Slave mode 0 UCMST_1 Master mode 1 UCSLA10 Slave addressing mode select 14 1 read-write UCSLA10_0 Address slave with 7-bit address 0 UCSLA10_1 Address slave with 10-bit address 1 UCSSEL eUSCI_B clock source select 6 2 read-write UCSSEL_0 UCLKI 0 UCSSEL_1 ACLK 1 UCSSEL_2 SMCLK 2 UCSSEL_3 SMCLK 3 UCSWRST Software reset enable 0 1 read-write UCSWRST_0 Disabled. eUSCI_B reset released for operation 0 UCSWRST_1 Enabled. eUSCI_B logic held in reset state 1 UCSYNC Synchronous mode enable 8 1 read-write UCSYNC_0 Asynchronous mode 0 UCSYNC_1 Synchronous mode 1 UCTR Transmitter/receiver 4 1 read-write UCTR_0 Receiver 0 UCTR_1 Transmitter 1 UCTXACK Transmit ACK condition in slave mode 5 1 read-write UCTXACK_0 Do not acknowledge the slave address 0 UCTXACK_1 Acknowledge the slave address 1 UCTXNACK Transmit a NACK 3 1 read-write UCTXNACK_0 Acknowledge normally 0 UCTXNACK_1 Generate NACK 1 UCTXSTP Transmit STOP condition in master mode 2 1 read-write UCTXSTP_0 No STOP generated 0 UCTXSTP_1 Generate STOP 1 UCTXSTT Transmit START condition in master mode 1 1 read-write UCTXSTT_0 Do not generate START condition 0 UCTXSTT_1 Generate START condition 1 UCBxCTLW1 CTLW1 eUSCI_Bx Control Word Register 1 0x2 16 read-write n 0x3 0xFFFF UCASTP Automatic STOP condition generation 2 2 read-write UCASTP_0 No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. 0 UCASTP_1 UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT 1 UCASTP_2 A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold 2 UCCLTO Clock low timeout select 6 2 read-write UCCLTO_0 Disable clock low timeout counter 0 UCCLTO_1 135 000 SYSCLK cycles (approximately 28 ms) 1 UCCLTO_2 150 000 SYSCLK cycles (approximately 31 ms) 2 UCCLTO_3 165 000 SYSCLK cycles (approximately 34 ms) 3 UCETXINT Early UCTXIFG0 8 1 read-write UCETXINT_0 UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit 0 UCETXINT_1 UCTXIFG0 is set for each START condition 1 UCGLIT Deglitch time 0 2 read-write UCGLIT_0 50 ns 0 UCGLIT_1 25 ns 1 UCGLIT_2 12.5 ns 2 UCGLIT_3 6.25 ns 3 UCSTPNACK ACK all master bytes 5 1 read-write UCSTPNACK_0 Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard) 0 UCSTPNACK_1 All bytes are acknowledged by the eUSCI_B when configured as master receiver 1 UCSWACK SW or HW ACK control 4 1 read-write UCSWACK_0 The address acknowledge of the slave is controlled by the eUSCI_B module 0 UCSWACK_1 The user needs to trigger the sending of the address ACK by issuing UCTXACK 1 UCBxI2COA0 I2COA0 eUSCI_Bx I2C Own Address 0 Register 0x14 16 read-write n 0x0 0xFFFF I2COA0 I2C own address 0 10 read-write UCGCEN General call response enable 15 1 read-write UCGCEN_0 Do not respond to a general call 0 UCGCEN_1 Respond to a general call 1 UCOAEN Own Address enable register 10 1 read-write UCOAEN_0 The slave address defined in I2COA0 is disabled 0 UCOAEN_1 The slave address defined in I2COA0 is enabled 1 UCBxI2COA1 I2COA1 eUSCI_Bx I2C Own Address 1 Register 0x16 16 read-write n 0x0 0xFFFF I2COA1 I2C own address 0 10 read-write UCOAEN Own Address enable register 10 1 read-write UCOAEN_0 The slave address defined in I2COA1 is disabled 0 UCOAEN_1 The slave address defined in I2COA1 is enabled 1 UCBxI2COA2 I2COA2 eUSCI_Bx I2C Own Address 2 Register 0x18 16 read-write n 0x0 0xFFFF I2COA2 I2C own address 0 10 read-write UCOAEN Own Address enable register 10 1 read-write UCOAEN_0 The slave address defined in I2COA2 is disabled 0 UCOAEN_1 The slave address defined in I2COA2 is enabled 1 UCBxI2COA3 I2COA3 eUSCI_Bx I2C Own Address 3 Register 0x1A 16 read-write n 0x0 0xFFFF I2COA3 I2C own address 0 10 read-write UCOAEN Own Address enable register 10 1 read-write UCOAEN_0 The slave address defined in I2COA3 is disabled 0 UCOAEN_1 The slave address defined in I2COA3 is enabled 1 UCBxI2CSA I2CSA eUSCI_Bx I2C Slave Address Register 0x20 16 read-write n 0x0 0xFFFF I2CSA I2C slave address 0 10 read-write UCBxIE IE eUSCI_Bx Interrupt Enable Register 0x2A 16 read-write n 0x0 0xFFFF UCALIE Arbitration lost interrupt enable 4 1 read-write UCALIE_0 Interrupt disabled 0 UCALIE_1 Interrupt enabled 1 UCBCNTIE Byte counter interrupt enable 6 1 read-write UCBCNTIE_0 Interrupt disabled 0 UCBCNTIE_1 Interrupt enabled 1 UCBIT9IE Bit position 9 interrupt enable 14 1 read-write UCBIT9IE_0 Interrupt disabled 0 UCBIT9IE_1 Interrupt enabled 1 UCCLTOIE Clock low timeout interrupt enable 7 1 read-write UCCLTOIE_0 Interrupt disabled 0 UCCLTOIE_1 Interrupt enabled 1 UCNACKIE Not-acknowledge interrupt enable 5 1 read-write UCNACKIE_0 Interrupt disabled 0 UCNACKIE_1 Interrupt enabled 1 UCRXIE0 Receive interrupt enable 0 0 1 read-write UCRXIE0_0 Interrupt disabled 0 UCRXIE0_1 Interrupt enabled 1 UCRXIE1 Receive interrupt enable 1 8 1 read-write UCRXIE1_0 Interrupt disabled 0 UCRXIE1_1 Interrupt enabled 1 UCRXIE2 Receive interrupt enable 2 10 1 read-write UCRXIE2_0 Interrupt disabled 0 UCRXIE2_1 Interrupt enabled 1 UCRXIE3 Receive interrupt enable 3 12 1 read-write UCRXIE3_0 Interrupt disabled 0 UCRXIE3_1 Interrupt enabled 1 UCSTPIE STOP condition interrupt enable 3 1 read-write UCSTPIE_0 Interrupt disabled 0 UCSTPIE_1 Interrupt enabled 1 UCSTTIE START condition interrupt enable 2 1 read-write UCSTTIE_0 Interrupt disabled 0 UCSTTIE_1 Interrupt enabled 1 UCTXIE0 Transmit interrupt enable 0 1 1 read-write UCTXIE0_0 Interrupt disabled 0 UCTXIE0_1 Interrupt enabled 1 UCTXIE1 Transmit interrupt enable 1 9 1 read-write UCTXIE1_0 Interrupt disabled 0 UCTXIE1_1 Interrupt enabled 1 UCTXIE2 Transmit interrupt enable 2 11 1 read-write UCTXIE2_0 Interrupt disabled 0 UCTXIE2_1 Interrupt enabled 1 UCTXIE3 Transmit interrupt enable 3 13 1 read-write UCTXIE3_0 Interrupt disabled 0 UCTXIE3_1 Interrupt enabled 1 UCBxIFG IFG eUSCI_Bx Interrupt Flag Register 0x2C 16 read-write n 0x2 0xFFFF UCALIFG Arbitration lost interrupt flag 4 1 read-write UCALIFG_0 No interrupt pending 0 UCALIFG_1 Interrupt pending 1 UCBCNTIFG Byte counter interrupt flag 6 1 read-write UCBCNTIFG_0 No interrupt pending 0 UCBCNTIFG_1 Interrupt pending 1 UCBIT9IFG Bit position 9 interrupt flag 14 1 read-write UCBIT9IFG_0 No interrupt pending 0 UCBIT9IFG_1 Interrupt pending 1 UCCLTOIFG Clock low timeout interrupt flag 7 1 read-write UCCLTOIFG_0 No interrupt pending 0 UCCLTOIFG_1 Interrupt pending 1 UCNACKIFG Not-acknowledge received interrupt flag 5 1 read-write UCNACKIFG_0 No interrupt pending 0 UCNACKIFG_1 Interrupt pending 1 UCRXIFG0 eUSCI_B receive interrupt flag 0 0 1 read-write UCRXIFG0_0 No interrupt pending 0 UCRXIFG0_1 Interrupt pending 1 UCRXIFG1 eUSCI_B receive interrupt flag 1 8 1 read-write UCRXIFG1_0 No interrupt pending 0 UCRXIFG1_1 Interrupt pending 1 UCRXIFG2 eUSCI_B receive interrupt flag 2 10 1 read-write UCRXIFG2_0 No interrupt pending 0 UCRXIFG2_1 Interrupt pending 1 UCRXIFG3 eUSCI_B receive interrupt flag 3 12 1 read-write UCRXIFG3_0 No interrupt pending 0 UCRXIFG3_1 Interrupt pending 1 UCSTPIFG STOP condition interrupt flag 3 1 read-write UCSTPIFG_0 No interrupt pending 0 UCSTPIFG_1 Interrupt pending 1 UCSTTIFG START condition interrupt flag 2 1 read-write UCSTTIFG_0 No interrupt pending 0 UCSTTIFG_1 Interrupt pending 1 UCTXIFG0 eUSCI_B transmit interrupt flag 0 1 1 read-write UCTXIFG0_0 No interrupt pending 0 UCTXIFG0_1 Interrupt pending 1 UCTXIFG1 eUSCI_B transmit interrupt flag 1 9 1 read-write UCTXIFG1_0 No interrupt pending 0 UCTXIFG1_1 Interrupt pending 1 UCTXIFG2 eUSCI_B transmit interrupt flag 2 11 1 read-write UCTXIFG2_0 No interrupt pending 0 UCTXIFG2_1 Interrupt pending 1 UCTXIFG3 eUSCI_B transmit interrupt flag 3 13 1 read-write UCTXIFG3_0 No interrupt pending 0 UCTXIFG3_1 Interrupt pending 1 UCBxIV IV eUSCI_Bx Interrupt Vector Register 0x2E 16 read-only n 0x0 0xFFFF UCIV eUSCI_B interrupt vector value 0 16 read-only UCIV_enum_read read UCIV_0 No interrupt pending 0 UCIV_10 Interrupt Source: Slave 3 Data received Interrupt Flag: UCRXIFG3 10 UCIV_12 Interrupt Source: Slave 3 Transmit buffer empty Interrupt Flag: UCTXIFG3 12 UCIV_14 Interrupt Source: Slave 2 Data received Interrupt Flag: UCRXIFG2 14 UCIV_16 Interrupt Source: Slave 2 Transmit buffer empty Interrupt Flag: UCTXIFG2 16 UCIV_18 Interrupt Source: Slave 1 Data received Interrupt Flag: UCRXIFG1 18 UCIV_2 Interrupt Source: Arbitration lost Interrupt Flag: UCALIFG Interrupt Priority: Highest 2 UCIV_20 Interrupt Source: Slave 1 Transmit buffer empty Interrupt Flag: UCTXIFG1 20 UCIV_22 Interrupt Source: Data received Interrupt Flag: UCRXIFG0 22 UCIV_24 Interrupt Source: Transmit buffer empty Interrupt Flag: UCTXIFG0 24 UCIV_26 Interrupt Source: Byte counter zero Interrupt Flag: UCBCNTIFG 26 UCIV_28 Interrupt Source: Clock low timeout Interrupt Flag: UCCLTOIFG 28 UCIV_30 Interrupt Source: Nineth bit position Interrupt Flag: UCBIT9IFG Priority: Lowest 30 UCIV_4 Interrupt Source: Not acknowledgment Interrupt Flag: UCNACKIFG 4 UCIV_6 Interrupt Source: Start condition received Interrupt Flag: UCSTTIFG 6 UCIV_8 Interrupt Source: Stop condition received Interrupt Flag: UCSTPIFG 8 UCBxRXBUF RXBUF eUSCI_Bx Receive Buffer Register 0xC 16 read-only n 0x0 0xFFFF UCRXBUF Receive data buffer 0 8 read-only UCBxSTATW STATW eUSCI_Bx Status Register 0x8 16 read-write n 0x0 0xFFFF UCBBUSY Bus busy 4 1 read-only UCBBUSY_enum_read read UCBBUSY_0 Bus inactive 0 UCBBUSY_1 Bus busy 1 UCBCNT Hardware byte counter value 8 8 read-only UCGC General call address received 5 1 read-only UCGC_enum_read read UCGC_0 No general call address received 0 UCGC_1 General call address received 1 UCSCLLOW SCL low 6 1 read-only UCSCLLOW_enum_read read UCSCLLOW_0 SCL is not held low 0 UCSCLLOW_1 SCL is held low 1 UCBxTBCNT TBCNT eUSCI_Bx Byte Counter Threshold Register 0xA 16 read-write n 0x0 0xFFFF UCTBCNT Byte counter threshold value 0 8 read-write UCBxTXBUF TXBUF eUSCI_Bx Transmit Buffer Register 0xE 16 read-write n 0x0 0xFFFF UCTXBUF Transmit data buffer 0 8 read-write FLCTL_A FLCTL_A FLCTL_A 0x40011000 0x0 0x260 registers n FLCTL_A_IRQ Flash Controller Interrupt 5 FLCTL_BANK0_INFO_WEPROT BANK0_INFO_WEPROT Information Memory Bank0 Write/Erase Protection Register 0xB0 32 read-write n 0xF 0xFFFFFFFF PROT0 Protects Sector 0 from program or erase 0 1 read-write PROT1 Protects Sector 1 from program or erase 1 1 read-write PROT2 Protects Sector 2 from program or erase 2 1 read-write PROT3 Protects Sector 3 from program or erase 3 1 read-write FLCTL_BANK0_MAIN_WEPROT BANK0_MAIN_WEPROT Main Memory Bank0 Write/Erase Protection Register 0xB4 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PROT0 Protects Sector 0 from program or erase 0 1 read-write PROT1 Protects Sector 1 from program or erase 1 1 read-write PROT10 Protects Sector 10 from program or erase 10 1 read-write PROT11 Protects Sector 11 from program or erase 11 1 read-write PROT12 Protects Sector 12 from program or erase 12 1 read-write PROT13 Protects Sector 13 from program or erase 13 1 read-write PROT14 Protects Sector 14 from program or erase 14 1 read-write PROT15 Protects Sector 15 from program or erase 15 1 read-write PROT16 Protects Sector 16 from program or erase 16 1 read-write PROT17 Protects Sector 17 from program or erase 17 1 read-write PROT18 Protects Sector 18 from program or erase 18 1 read-write PROT19 Protects Sector 19 from program or erase 19 1 read-write PROT2 Protects Sector 2 from program or erase 2 1 read-write PROT20 Protects Sector 20 from program or erase 20 1 read-write PROT21 Protects Sector 21 from program or erase 21 1 read-write PROT22 Protects Sector 22 from program or erase 22 1 read-write PROT23 Protects Sector 23 from program or erase 23 1 read-write PROT24 Protects Sector 24 from program or erase 24 1 read-write PROT25 Protects Sector 25 from program or erase 25 1 read-write PROT26 Protects Sector 26 from program or erase 26 1 read-write PROT27 Protects Sector 27 from program or erase 27 1 read-write PROT28 Protects Sector 28 from program or erase 28 1 read-write PROT29 Protects Sector 29 from program or erase 29 1 read-write PROT3 Protects Sector 3 from program or erase 3 1 read-write PROT30 Protects Sector 30 from program or erase 30 1 read-write PROT31 Protects Sector 31 from program or erase 31 1 read-write PROT4 Protects Sector 4 from program or erase 4 1 read-write PROT5 Protects Sector 5 from program or erase 5 1 read-write PROT6 Protects Sector 6 from program or erase 6 1 read-write PROT7 Protects Sector 7 from program or erase 7 1 read-write PROT8 Protects Sector 8 from program or erase 8 1 read-write PROT9 Protects Sector 9 from program or erase 9 1 read-write FLCTL_BANK0_MAIN_WEPROT0 BANK0_MAIN_WEPROT0 Main Memory Bank0 Write/Erase Protection Register 0 0x200 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PROT0 Protects Sector 0 from program or erase 0 1 read-write PROT1 Protects Sector 1 from program or erase 1 1 read-write PROT10 Protects Sector 10 from program or erase 10 1 read-write PROT11 Protects Sector 11 from program or erase 11 1 read-write PROT12 Protects Sector 12 from program or erase 12 1 read-write PROT13 Protects Sector 13 from program or erase 13 1 read-write PROT14 Protects Sector 14 from program or erase 14 1 read-write PROT15 Protects Sector 15 from program or erase 15 1 read-write PROT16 Protects Sector 16 from program or erase 16 1 read-write PROT17 Protects Sector 17 from program or erase 17 1 read-write PROT18 Protects Sector 18 from program or erase 18 1 read-write PROT19 Protects Sector 19 from program or erase 19 1 read-write PROT2 Protects Sector 2 from program or erase 2 1 read-write PROT20 Protects Sector 20 from program or erase 20 1 read-write PROT21 Protects Sector 21 from program or erase 21 1 read-write PROT22 Protects Sector 22 from program or erase 22 1 read-write PROT23 Protects Sector 23 from program or erase 23 1 read-write PROT24 Protects Sector 24 from program or erase 24 1 read-write PROT25 Protects Sector 25 from program or erase 25 1 read-write PROT26 Protects Sector 26 from program or erase 26 1 read-write PROT27 Protects Sector 27 from program or erase 27 1 read-write PROT28 Protects Sector 28 from program or erase 28 1 read-write PROT29 Protects Sector 29 from program or erase 29 1 read-write PROT3 Protects Sector 3 from program or erase 3 1 read-write PROT30 Protects Sector 30 from program or erase 30 1 read-write PROT31 Protects Sector 31 from program or erase 31 1 read-write PROT4 Protects Sector 4 from program or erase 4 1 read-write PROT5 Protects Sector 5 from program or erase 5 1 read-write PROT6 Protects Sector 6 from program or erase 6 1 read-write PROT7 Protects Sector 7 from program or erase 7 1 read-write PROT8 Protects Sector 8 from program or erase 8 1 read-write PROT9 Protects Sector 9 from program or erase 9 1 read-write FLCTL_BANK0_MAIN_WEPROT1 BANK0_MAIN_WEPROT1 Main Memory Bank0 Write/Erase Protection Register 1 0x204 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PROT32 Protects Sector 32 from program or erase 0 1 read-write PROT33 Protects Sector 33 from program or erase 1 1 read-write PROT34 Protects Sector 34 from program or erase 2 1 read-write PROT35 Protects Sector 35 from program or erase 3 1 read-write PROT36 Protects Sector 36 from program or erase 4 1 read-write PROT37 Protects Sector 37 from program or erase 5 1 read-write PROT38 Protects Sector 38 from program or erase 6 1 read-write PROT39 Protects Sector 39 from program or erase 7 1 read-write PROT40 Protects Sector 40 from program or erase 8 1 read-write PROT41 Protects Sector 41 from program or erase 9 1 read-write PROT42 Protects Sector 42 from program or erase 10 1 read-write PROT43 Protects Sector 43 from program or erase 11 1 read-write PROT44 Protects Sector 44 from program or erase 12 1 read-write PROT45 Protects Sector 45 from program or erase 13 1 read-write PROT46 Protects Sector 46 from program or erase 14 1 read-write PROT47 Protects Sector 47 from program or erase 15 1 read-write PROT48 Protects Sector 48 from program or erase 16 1 read-write PROT49 Protects Sector 49 from program or erase 17 1 read-write PROT50 Protects Sector 50 from program or erase 18 1 read-write PROT51 Protects Sector 51 from program or erase 19 1 read-write PROT52 Protects Sector 52 from program or erase 20 1 read-write PROT53 Protects Sector 53 from program or erase 21 1 read-write PROT54 Protects Sector 54 from program or erase 22 1 read-write PROT55 Protects Sector 55 from program or erase 23 1 read-write PROT56 Protects Sector 56 from program or erase 24 1 read-write PROT57 Protects Sector 57 from program or erase 25 1 read-write PROT58 Protects Sector 58 from program or erase 26 1 read-write PROT59 Protects Sector 59 from program or erase 27 1 read-write PROT60 Protects Sector 60 from program or erase 28 1 read-write PROT61 Protects Sector 61 from program or erase 29 1 read-write PROT62 Protects Sector 62 from program or erase 30 1 read-write PROT63 Protects Sector 63 from program or erase 31 1 read-write FLCTL_BANK0_MAIN_WEPROT2 BANK0_MAIN_WEPROT2 Main Memory Bank0 Write/Erase Protection Register 2 0x208 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PROT64 Protects Sector 64 from program or erase 0 1 read-write PROT65 Protects Sector 65 from program or erase 1 1 read-write PROT66 Protects Sector 66 from program or erase 2 1 read-write PROT67 Protects Sector 67 from program or erase 3 1 read-write PROT68 Protects Sector 68 from program or erase 4 1 read-write PROT69 Protects Sector 69 from program or erase 5 1 read-write PROT70 Protects Sector 70 from program or erase 6 1 read-write PROT71 Protects Sector 71 from program or erase 7 1 read-write PROT72 Protects Sector 72 from program or erase 8 1 read-write PROT73 Protects Sector 73 from program or erase 9 1 read-write PROT74 Protects Sector 74 from program or erase 10 1 read-write PROT75 Protects Sector 75 from program or erase 11 1 read-write PROT76 Protects Sector 76 from program or erase 12 1 read-write PROT77 Protects Sector 77 from program or erase 13 1 read-write PROT78 Protects Sector 78 from program or erase 14 1 read-write PROT79 Protects Sector 79 from program or erase 15 1 read-write PROT80 Protects Sector 80 from program or erase 16 1 read-write PROT81 Protects Sector 81 from program or erase 17 1 read-write PROT82 Protects Sector 82 from program or erase 18 1 read-write PROT83 Protects Sector 83 from program or erase 19 1 read-write PROT84 Protects Sector 84 from program or erase 20 1 read-write PROT85 Protects Sector 85 from program or erase 21 1 read-write PROT86 Protects Sector 86 from program or erase 22 1 read-write PROT87 Protects Sector 87 from program or erase 23 1 read-write PROT88 Protects Sector 88 from program or erase 24 1 read-write PROT89 Protects Sector 89 from program or erase 25 1 read-write PROT90 Protects Sector 90 from program or erase 26 1 read-write PROT91 Protects Sector 91 from program or erase 27 1 read-write PROT92 Protects Sector 92 from program or erase 28 1 read-write PROT93 Protects Sector 93 from program or erase 29 1 read-write PROT94 Protects Sector 94 from program or erase 30 1 read-write PROT95 Protects Sector 95 from program or erase 31 1 read-write FLCTL_BANK0_MAIN_WEPROT3 BANK0_MAIN_WEPROT3 Main Memory Bank0 Write/Erase Protection Register 3 0x20C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PROT100 Protects Sector 100 from program or erase 4 1 read-write PROT101 Protects Sector 101 from program or erase 5 1 read-write PROT102 Protects Sector 102 from program or erase 6 1 read-write PROT103 Protects Sector 103 from program or erase 7 1 read-write PROT104 Protects Sector 104 from program or erase 8 1 read-write PROT105 Protects Sector 105 from program or erase 9 1 read-write PROT106 Protects Sector 106 from program or erase 10 1 read-write PROT107 Protects Sector 107 from program or erase 11 1 read-write PROT108 Protects Sector 108 from program or erase 12 1 read-write PROT109 Protects Sector 109 from program or erase 13 1 read-write PROT110 Protects Sector 110 from program or erase 14 1 read-write PROT111 Protects Sector 111 from program or erase 15 1 read-write PROT112 Protects Sector 112 from program or erase 16 1 read-write PROT113 Protects Sector 113 from program or erase 17 1 read-write PROT114 Protects Sector 114 from program or erase 18 1 read-write PROT115 Protects Sector 115 from program or erase 19 1 read-write PROT116 Protects Sector 116 from program or erase 20 1 read-write PROT117 Protects Sector 117 from program or erase 21 1 read-write PROT118 Protects Sector 118 from program or erase 22 1 read-write PROT119 Protects Sector 119 from program or erase 23 1 read-write PROT120 Protects Sector 120 from program or erase 24 1 read-write PROT121 Protects Sector 121 from program or erase 25 1 read-write PROT122 Protects Sector 122 from program or erase 26 1 read-write PROT123 Protects Sector 123 from program or erase 27 1 read-write PROT124 Protects Sector 124 from program or erase 28 1 read-write PROT125 Protects Sector 125 from program or erase 29 1 read-write PROT126 Protects Sector 126 from program or erase 30 1 read-write PROT127 Protects Sector 127 from program or erase 31 1 read-write PROT96 Protects Sector 96 from program or erase 0 1 read-write PROT97 Protects Sector 97 from program or erase 1 1 read-write PROT98 Protects Sector 98 from program or erase 2 1 read-write PROT99 Protects Sector 99 from program or erase 3 1 read-write FLCTL_BANK0_MAIN_WEPROT4 BANK0_MAIN_WEPROT4 Main Memory Bank0 Write/Erase Protection Register 4 0x210 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PROT128 Protects Sector 128 from program or erase 0 1 read-write PROT129 Protects Sector 129 from program or erase 1 1 read-write PROT130 Protects Sector 130 from program or erase 2 1 read-write PROT131 Protects Sector 131 from program or erase 3 1 read-write PROT132 Protects Sector 132 from program or erase 4 1 read-write PROT133 Protects Sector 133 from program or erase 5 1 read-write PROT134 Protects Sector 134 from program or erase 6 1 read-write PROT135 Protects Sector 135 from program or erase 7 1 read-write PROT136 Protects Sector 136 from program or erase 8 1 read-write PROT137 Protects Sector 137 from program or erase 9 1 read-write PROT138 Protects Sector 138 from program or erase 10 1 read-write PROT139 Protects Sector 139 from program or erase 11 1 read-write PROT140 Protects Sector 140 from program or erase 12 1 read-write PROT141 Protects Sector 141 from program or erase 13 1 read-write PROT142 Protects Sector 142 from program or erase 14 1 read-write PROT143 Protects Sector 143 from program or erase 15 1 read-write PROT144 Protects Sector 144 from program or erase 16 1 read-write PROT145 Protects Sector 145 from program or erase 17 1 read-write PROT146 Protects Sector 146 from program or erase 18 1 read-write PROT147 Protects Sector 147 from program or erase 19 1 read-write PROT148 Protects Sector 148 from program or erase 20 1 read-write PROT149 Protects Sector 149 from program or erase 21 1 read-write PROT150 Protects Sector 150 from program or erase 22 1 read-write PROT151 Protects Sector 151 from program or erase 23 1 read-write PROT152 Protects Sector 152 from program or erase 24 1 read-write PROT153 Protects Sector 153 from program or erase 25 1 read-write PROT154 Protects Sector 154 from program or erase 26 1 read-write PROT155 Protects Sector 155 from program or erase 27 1 read-write PROT156 Protects Sector 156 from program or erase 28 1 read-write PROT157 Protects Sector 157 from program or erase 29 1 read-write PROT158 Protects Sector 158 from program or erase 30 1 read-write PROT159 Protects Sector 159 from program or erase 31 1 read-write FLCTL_BANK0_MAIN_WEPROT5 BANK0_MAIN_WEPROT5 Main Memory Bank0 Write/Erase Protection Register 5 0x214 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PROT160 Protects Sector 160 from program or erase 0 1 read-write PROT161 Protects Sector 161 from program or erase 1 1 read-write PROT162 Protects Sector 162 from program or erase 2 1 read-write PROT163 Protects Sector 163 from program or erase 3 1 read-write PROT164 Protects Sector 164 from program or erase 4 1 read-write PROT165 Protects Sector 165 from program or erase 5 1 read-write PROT166 Protects Sector 166 from program or erase 6 1 read-write PROT167 Protects Sector 167 from program or erase 7 1 read-write PROT168 Protects Sector 168 from program or erase 8 1 read-write PROT169 Protects Sector 169 from program or erase 9 1 read-write PROT170 Protects Sector 170 from program or erase 10 1 read-write PROT171 Protects Sector 171 from program or erase 11 1 read-write PROT172 Protects Sector 172 from program or erase 12 1 read-write PROT173 Protects Sector 173 from program or erase 13 1 read-write PROT174 Protects Sector 174 from program or erase 14 1 read-write PROT175 Protects Sector 175 from program or erase 15 1 read-write PROT176 Protects Sector 176 from program or erase 16 1 read-write PROT177 Protects Sector 177 from program or erase 17 1 read-write PROT178 Protects Sector 178 from program or erase 18 1 read-write PROT179 Protects Sector 179 from program or erase 19 1 read-write PROT180 Protects Sector 180 from program or erase 20 1 read-write PROT181 Protects Sector 181 from program or erase 21 1 read-write PROT182 Protects Sector 182 from program or erase 22 1 read-write PROT183 Protects Sector 183 from program or erase 23 1 read-write PROT184 Protects Sector 184 from program or erase 24 1 read-write PROT185 Protects Sector 185 from program or erase 25 1 read-write PROT186 Protects Sector 186 from program or erase 26 1 read-write PROT187 Protects Sector 187 from program or erase 27 1 read-write PROT188 Protects Sector 188 from program or erase 28 1 read-write PROT189 Protects Sector 189 from program or erase 29 1 read-write PROT190 Protects Sector 190 from program or erase 30 1 read-write PROT191 Protects Sector 191 from program or erase 31 1 read-write FLCTL_BANK0_MAIN_WEPROT6 BANK0_MAIN_WEPROT6 Main Memory Bank0 Write/Erase Protection Register 6 0x218 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PROT192 Protects Sector 192 from program or erase 0 1 read-write PROT193 Protects Sector 193 from program or erase 1 1 read-write PROT194 Protects Sector 194 from program or erase 2 1 read-write PROT195 Protects Sector 195 from program or erase 3 1 read-write PROT196 Protects Sector 196 from program or erase 4 1 read-write PROT197 Protects Sector 197 from program or erase 5 1 read-write PROT198 Protects Sector 198 from program or erase 6 1 read-write PROT199 Protects Sector 199 from program or erase 7 1 read-write PROT200 Protects Sector 200 from program or erase 8 1 read-write PROT201 Protects Sector 201 from program or erase 9 1 read-write PROT202 Protects Sector 202 from program or erase 10 1 read-write PROT203 Protects Sector 203 from program or erase 11 1 read-write PROT204 Protects Sector 204 from program or erase 12 1 read-write PROT205 Protects Sector 205 from program or erase 13 1 read-write PROT206 Protects Sector 206 from program or erase 14 1 read-write PROT207 Protects Sector 207 from program or erase 15 1 read-write PROT208 Protects Sector 208 from program or erase 16 1 read-write PROT209 Protects Sector 209 from program or erase 17 1 read-write PROT210 Protects Sector 210 from program or erase 18 1 read-write PROT211 Protects Sector 211 from program or erase 19 1 read-write PROT212 Protects Sector 212 from program or erase 20 1 read-write PROT213 Protects Sector 213 from program or erase 21 1 read-write PROT214 Protects Sector 214 from program or erase 22 1 read-write PROT215 Protects Sector 215 from program or erase 23 1 read-write PROT216 Protects Sector 216 from program or erase 24 1 read-write PROT217 Protects Sector 217 from program or erase 25 1 read-write PROT218 Protects Sector 218 from program or erase 26 1 read-write PROT219 Protects Sector 219 from program or erase 27 1 read-write PROT220 Protects Sector 220 from program or erase 28 1 read-write PROT221 Protects Sector 221 from program or erase 29 1 read-write PROT222 Protects Sector 222 from program or erase 30 1 read-write PROT223 Protects Sector 223 from program or erase 31 1 read-write FLCTL_BANK0_MAIN_WEPROT7 BANK0_MAIN_WEPROT7 Main Memory Bank0 Write/Erase Protection Register 7 0x21C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PROT224 Protects Sector 224 from program or erase 0 1 read-write PROT225 Protects Sector 225 from program or erase 1 1 read-write PROT226 Protects Sector 226 from program or erase 2 1 read-write PROT227 Protects Sector 227 from program or erase 3 1 read-write PROT228 Protects Sector 228 from program or erase 4 1 read-write PROT229 Protects Sector 229 from program or erase 5 1 read-write PROT230 Protects Sector 230 from program or erase 6 1 read-write PROT231 Protects Sector 231 from program or erase 7 1 read-write PROT232 Protects Sector 232 from program or erase 8 1 read-write PROT233 Protects Sector 233 from program or erase 9 1 read-write PROT234 Protects Sector 234 from program or erase 10 1 read-write PROT235 Protects Sector 235 from program or erase 11 1 read-write PROT236 Protects Sector 236 from program or erase 12 1 read-write PROT237 Protects Sector 237 from program or erase 13 1 read-write PROT238 Protects Sector 238 from program or erase 14 1 read-write PROT239 Protects Sector 239 from program or erase 15 1 read-write PROT240 Protects Sector 240 from program or erase 16 1 read-write PROT241 Protects Sector 241 from program or erase 17 1 read-write PROT242 Protects Sector 242 from program or erase 18 1 read-write PROT243 Protects Sector 243 from program or erase 19 1 read-write PROT244 Protects Sector 244 from program or erase 20 1 read-write PROT245 Protects Sector 245 from program or erase 21 1 read-write PROT246 Protects Sector 246 from program or erase 22 1 read-write PROT247 Protects Sector 247 from program or erase 23 1 read-write PROT248 Protects Sector 248 from program or erase 24 1 read-write PROT249 Protects Sector 249 from program or erase 25 1 read-write PROT250 Protects Sector 250 from program or erase 26 1 read-write PROT251 Protects Sector 251 from program or erase 27 1 read-write PROT252 Protects Sector 252 from program or erase 28 1 read-write PROT253 Protects Sector 253 from program or erase 29 1 read-write PROT254 Protects Sector 254 from program or erase 30 1 read-write PROT255 Protects Sector 255 from program or erase 31 1 read-write FLCTL_BANK0_RDCTL BANK0_RDCTL Bank0 Read Control Register 0x10 32 read-write n 0x0 0xFFFFFFFF BUFD Enables read buffering feature for data reads to this Bank 5 1 read-write BUFI Enables read buffering feature for instruction fetches to this Bank 4 1 read-write RD_MODE Flash read mode control setting for Bank 0 0 4 read-write RD_MODE_0 Normal read mode 0 RD_MODE_1 Read Margin 0 1 RD_MODE_10 Read Margin 1B 10 RD_MODE_2 Read Margin 1 2 RD_MODE_3 Program Verify 3 RD_MODE_4 Erase Verify 4 RD_MODE_5 Leakage Verify 5 RD_MODE_9 Read Margin 0B 9 RD_MODE_STATUS Read mode 16 4 read-only RD_MODE_STATUS_0 Normal read mode 0 RD_MODE_STATUS_1 Read Margin 0 1 RD_MODE_STATUS_10 Read Margin 1B 10 RD_MODE_STATUS_2 Read Margin 1 2 RD_MODE_STATUS_3 Program Verify 3 RD_MODE_STATUS_4 Erase Verify 4 RD_MODE_STATUS_5 Leakage Verify 5 RD_MODE_STATUS_9 Read Margin 0B 9 WAIT Number of wait states for read 12 4 read-write WAIT_0 0 wait states 0 WAIT_1 1 wait states 1 WAIT_10 10 wait states 10 WAIT_11 11 wait states 11 WAIT_12 12 wait states 12 WAIT_13 13 wait states 13 WAIT_14 14 wait states 14 WAIT_15 15 wait states 15 WAIT_2 2 wait states 2 WAIT_3 3 wait states 3 WAIT_4 4 wait states 4 WAIT_5 5 wait states 5 WAIT_6 6 wait states 6 WAIT_7 7 wait states 7 WAIT_8 8 wait states 8 WAIT_9 9 wait states 9 FLCTL_BANK1_INFO_WEPROT BANK1_INFO_WEPROT Information Memory Bank1 Write/Erase Protection Register 0xC0 32 read-write n 0xF 0xFFFFFFFF PROT0 Protects Sector 0 from program or erase operations 0 1 read-write PROT1 Protects Sector 1 from program or erase operations 1 1 read-write PROT2 Protects Sector 2 from program or erase 2 1 read-write PROT3 Protects Sector 3 from program or erase 3 1 read-write FLCTL_BANK1_MAIN_WEPROT BANK1_MAIN_WEPROT Main Memory Bank1 Write/Erase Protection Register 0xC4 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PROT0 Protects Sector 0 from program or erase operations 0 1 read-write PROT1 Protects Sector 1 from program or erase operations 1 1 read-write PROT10 Protects Sector 10 from program or erase operations 10 1 read-write PROT11 Protects Sector 11 from program or erase operations 11 1 read-write PROT12 Protects Sector 12 from program or erase operations 12 1 read-write PROT13 Protects Sector 13 from program or erase operations 13 1 read-write PROT14 Protects Sector 14 from program or erase operations 14 1 read-write PROT15 Protects Sector 15 from program or erase operations 15 1 read-write PROT16 Protects Sector 16 from program or erase operations 16 1 read-write PROT17 Protects Sector 17 from program or erase operations 17 1 read-write PROT18 Protects Sector 18 from program or erase operations 18 1 read-write PROT19 Protects Sector 19 from program or erase operations 19 1 read-write PROT2 Protects Sector 2 from program or erase operations 2 1 read-write PROT20 Protects Sector 20 from program or erase operations 20 1 read-write PROT21 Protects Sector 21 from program or erase operations 21 1 read-write PROT22 Protects Sector 22 from program or erase operations 22 1 read-write PROT23 Protects Sector 23 from program or erase operations 23 1 read-write PROT24 Protects Sector 24 from program or erase operations 24 1 read-write PROT25 Protects Sector 25 from program or erase operations 25 1 read-write PROT26 Protects Sector 26 from program or erase operations 26 1 read-write PROT27 Protects Sector 27 from program or erase operations 27 1 read-write PROT28 Protects Sector 28 from program or erase operations 28 1 read-write PROT29 Protects Sector 29 from program or erase operations 29 1 read-write PROT3 Protects Sector 3 from program or erase operations 3 1 read-write PROT30 Protects Sector 30 from program or erase operations 30 1 read-write PROT31 Protects Sector 31 from program or erase operations 31 1 read-write PROT4 Protects Sector 4 from program or erase operations 4 1 read-write PROT5 Protects Sector 5 from program or erase operations 5 1 read-write PROT6 Protects Sector 6 from program or erase operations 6 1 read-write PROT7 Protects Sector 7 from program or erase operations 7 1 read-write PROT8 Protects Sector 8 from program or erase operations 8 1 read-write PROT9 Protects Sector 9 from program or erase operations 9 1 read-write FLCTL_BANK1_MAIN_WEPROT0 BANK1_MAIN_WEPROT0 Main Memory Bank1 Write/Erase Protection Register 0 0x240 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PROT0 Protects Sector 0 from program or erase 0 1 read-write PROT1 Protects Sector 1 from program or erase 1 1 read-write PROT10 Protects Sector 10 from program or erase 10 1 read-write PROT11 Protects Sector 11 from program or erase 11 1 read-write PROT12 Protects Sector 12 from program or erase 12 1 read-write PROT13 Protects Sector 13 from program or erase 13 1 read-write PROT14 Protects Sector 14 from program or erase 14 1 read-write PROT15 Protects Sector 15 from program or erase 15 1 read-write PROT16 Protects Sector 16 from program or erase 16 1 read-write PROT17 Protects Sector 17 from program or erase 17 1 read-write PROT18 Protects Sector 18 from program or erase 18 1 read-write PROT19 Protects Sector 19 from program or erase 19 1 read-write PROT2 Protects Sector 2 from program or erase 2 1 read-write PROT20 Protects Sector 20 from program or erase 20 1 read-write PROT21 Protects Sector 21 from program or erase 21 1 read-write PROT22 Protects Sector 22 from program or erase 22 1 read-write PROT23 Protects Sector 23 from program or erase 23 1 read-write PROT24 Protects Sector 24 from program or erase 24 1 read-write PROT25 Protects Sector 25 from program or erase 25 1 read-write PROT26 Protects Sector 26 from program or erase 26 1 read-write PROT27 Protects Sector 27 from program or erase 27 1 read-write PROT28 Protects Sector 28 from program or erase 28 1 read-write PROT29 Protects Sector 29 from program or erase 29 1 read-write PROT3 Protects Sector 3 from program or erase 3 1 read-write PROT30 Protects Sector 30 from program or erase 30 1 read-write PROT31 Protects Sector 31 from program or erase 31 1 read-write PROT4 Protects Sector 4 from program or erase 4 1 read-write PROT5 Protects Sector 5 from program or erase 5 1 read-write PROT6 Protects Sector 6 from program or erase 6 1 read-write PROT7 Protects Sector 7 from program or erase 7 1 read-write PROT8 Protects Sector 8 from program or erase 8 1 read-write PROT9 Protects Sector 9 from program or erase 9 1 read-write FLCTL_BANK1_MAIN_WEPROT1 BANK1_MAIN_WEPROT1 Main Memory Bank1 Write/Erase Protection Register 1 0x244 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PROT32 Protects Sector 32 from program or erase 0 1 read-write PROT33 Protects Sector 33 from program or erase 1 1 read-write PROT34 Protects Sector 34 from program or erase 2 1 read-write PROT35 Protects Sector 35 from program or erase 3 1 read-write PROT36 Protects Sector 36 from program or erase 4 1 read-write PROT37 Protects Sector 37 from program or erase 5 1 read-write PROT38 Protects Sector 38 from program or erase 6 1 read-write PROT39 Protects Sector 39 from program or erase 7 1 read-write PROT40 Protects Sector 40 from program or erase 8 1 read-write PROT41 Protects Sector 41 from program or erase 9 1 read-write PROT42 Protects Sector 42 from program or erase 10 1 read-write PROT43 Protects Sector 43 from program or erase 11 1 read-write PROT44 Protects Sector 44 from program or erase 12 1 read-write PROT45 Protects Sector 45 from program or erase 13 1 read-write PROT46 Protects Sector 46 from program or erase 14 1 read-write PROT47 Protects Sector 47 from program or erase 15 1 read-write PROT48 Protects Sector 48 from program or erase 16 1 read-write PROT49 Protects Sector 49 from program or erase 17 1 read-write PROT50 Protects Sector 50 from program or erase 18 1 read-write PROT51 Protects Sector 51 from program or erase 19 1 read-write PROT52 Protects Sector 52 from program or erase 20 1 read-write PROT53 Protects Sector 53 from program or erase 21 1 read-write PROT54 Protects Sector 54 from program or erase 22 1 read-write PROT55 Protects Sector 55 from program or erase 23 1 read-write PROT56 Protects Sector 56 from program or erase 24 1 read-write PROT57 Protects Sector 57 from program or erase 25 1 read-write PROT58 Protects Sector 58 from program or erase 26 1 read-write PROT59 Protects Sector 59 from program or erase 27 1 read-write PROT60 Protects Sector 60 from program or erase 28 1 read-write PROT61 Protects Sector 61 from program or erase 29 1 read-write PROT62 Protects Sector 62 from program or erase 30 1 read-write PROT63 Protects Sector 63 from program or erase 31 1 read-write FLCTL_BANK1_MAIN_WEPROT2 BANK1_MAIN_WEPROT2 Main Memory Bank1 Write/Erase Protection Register 2 0x248 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PROT64 Protects Sector 64 from program or erase 0 1 read-write PROT65 Protects Sector 65 from program or erase 1 1 read-write PROT66 Protects Sector 66 from program or erase 2 1 read-write PROT67 Protects Sector 67 from program or erase 3 1 read-write PROT68 Protects Sector 68 from program or erase 4 1 read-write PROT69 Protects Sector 69 from program or erase 5 1 read-write PROT70 Protects Sector 70 from program or erase 6 1 read-write PROT71 Protects Sector 71 from program or erase 7 1 read-write PROT72 Protects Sector 72 from program or erase 8 1 read-write PROT73 Protects Sector 73 from program or erase 9 1 read-write PROT74 Protects Sector 74 from program or erase 10 1 read-write PROT75 Protects Sector 75 from program or erase 11 1 read-write PROT76 Protects Sector 76 from program or erase 12 1 read-write PROT77 Protects Sector 77 from program or erase 13 1 read-write PROT78 Protects Sector 78 from program or erase 14 1 read-write PROT79 Protects Sector 79 from program or erase 15 1 read-write PROT80 Protects Sector 80 from program or erase 16 1 read-write PROT81 Protects Sector 81 from program or erase 17 1 read-write PROT82 Protects Sector 82 from program or erase 18 1 read-write PROT83 Protects Sector 83 from program or erase 19 1 read-write PROT84 Protects Sector 84 from program or erase 20 1 read-write PROT85 Protects Sector 85 from program or erase 21 1 read-write PROT86 Protects Sector 86 from program or erase 22 1 read-write PROT87 Protects Sector 87 from program or erase 23 1 read-write PROT88 Protects Sector 88 from program or erase 24 1 read-write PROT89 Protects Sector 89 from program or erase 25 1 read-write PROT90 Protects Sector 90 from program or erase 26 1 read-write PROT91 Protects Sector 91 from program or erase 27 1 read-write PROT92 Protects Sector 92 from program or erase 28 1 read-write PROT93 Protects Sector 93 from program or erase 29 1 read-write PROT94 Protects Sector 94 from program or erase 30 1 read-write PROT95 Protects Sector 95 from program or erase 31 1 read-write FLCTL_BANK1_MAIN_WEPROT3 BANK1_MAIN_WEPROT3 Main Memory Bank1 Write/Erase Protection Register 3 0x24C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PROT100 Protects Sector 100 from program or erase 4 1 read-write PROT101 Protects Sector 101 from program or erase 5 1 read-write PROT102 Protects Sector 102 from program or erase 6 1 read-write PROT103 Protects Sector 103 from program or erase 7 1 read-write PROT104 Protects Sector 104 from program or erase 8 1 read-write PROT105 Protects Sector 105 from program or erase 9 1 read-write PROT106 Protects Sector 106 from program or erase 10 1 read-write PROT107 Protects Sector 107 from program or erase 11 1 read-write PROT108 Protects Sector 108 from program or erase 12 1 read-write PROT109 Protects Sector 109 from program or erase 13 1 read-write PROT110 Protects Sector 110 from program or erase 14 1 read-write PROT111 Protects Sector 111 from program or erase 15 1 read-write PROT112 Protects Sector 112 from program or erase 16 1 read-write PROT113 Protects Sector 113 from program or erase 17 1 read-write PROT114 Protects Sector 114 from program or erase 18 1 read-write PROT115 Protects Sector 115 from program or erase 19 1 read-write PROT116 Protects Sector 116 from program or erase 20 1 read-write PROT117 Protects Sector 117 from program or erase 21 1 read-write PROT118 Protects Sector 118 from program or erase 22 1 read-write PROT119 Protects Sector 119 from program or erase 23 1 read-write PROT120 Protects Sector 120 from program or erase 24 1 read-write PROT121 Protects Sector 121 from program or erase 25 1 read-write PROT122 Protects Sector 122 from program or erase 26 1 read-write PROT123 Protects Sector 123 from program or erase 27 1 read-write PROT124 Protects Sector 124 from program or erase 28 1 read-write PROT125 Protects Sector 125 from program or erase 29 1 read-write PROT126 Protects Sector 126 from program or erase 30 1 read-write PROT127 Protects Sector 127 from program or erase 31 1 read-write PROT96 Protects Sector 96 from program or erase 0 1 read-write PROT97 Protects Sector 97 from program or erase 1 1 read-write PROT98 Protects Sector 98 from program or erase 2 1 read-write PROT99 Protects Sector 99 from program or erase 3 1 read-write FLCTL_BANK1_MAIN_WEPROT4 BANK1_MAIN_WEPROT4 Main Memory Bank1 Write/Erase Protection Register 4 0x250 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PROT128 Protects Sector 128 from program or erase 0 1 read-write PROT129 Protects Sector 129 from program or erase 1 1 read-write PROT130 Protects Sector 130 from program or erase 2 1 read-write PROT131 Protects Sector 131 from program or erase 3 1 read-write PROT132 Protects Sector 132 from program or erase 4 1 read-write PROT133 Protects Sector 133 from program or erase 5 1 read-write PROT134 Protects Sector 134 from program or erase 6 1 read-write PROT135 Protects Sector 135 from program or erase 7 1 read-write PROT136 Protects Sector 136 from program or erase 8 1 read-write PROT137 Protects Sector 137 from program or erase 9 1 read-write PROT138 Protects Sector 138 from program or erase 10 1 read-write PROT139 Protects Sector 139 from program or erase 11 1 read-write PROT140 Protects Sector 140 from program or erase 12 1 read-write PROT141 Protects Sector 141 from program or erase 13 1 read-write PROT142 Protects Sector 142 from program or erase 14 1 read-write PROT143 Protects Sector 143 from program or erase 15 1 read-write PROT144 Protects Sector 144 from program or erase 16 1 read-write PROT145 Protects Sector 145 from program or erase 17 1 read-write PROT146 Protects Sector 146 from program or erase 18 1 read-write PROT147 Protects Sector 147 from program or erase 19 1 read-write PROT148 Protects Sector 148 from program or erase 20 1 read-write PROT149 Protects Sector 149 from program or erase 21 1 read-write PROT150 Protects Sector 150 from program or erase 22 1 read-write PROT151 Protects Sector 151 from program or erase 23 1 read-write PROT152 Protects Sector 152 from program or erase 24 1 read-write PROT153 Protects Sector 153 from program or erase 25 1 read-write PROT154 Protects Sector 154 from program or erase 26 1 read-write PROT155 Protects Sector 155 from program or erase 27 1 read-write PROT156 Protects Sector 156 from program or erase 28 1 read-write PROT157 Protects Sector 157 from program or erase 29 1 read-write PROT158 Protects Sector 158 from program or erase 30 1 read-write PROT159 Protects Sector 159 from program or erase 31 1 read-write FLCTL_BANK1_MAIN_WEPROT5 BANK1_MAIN_WEPROT5 Main Memory Bank1 Write/Erase Protection Register 5 0x254 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PROT160 Protects Sector 160 from program or erase 0 1 read-write PROT161 Protects Sector 161 from program or erase 1 1 read-write PROT162 Protects Sector 162 from program or erase 2 1 read-write PROT163 Protects Sector 163 from program or erase 3 1 read-write PROT164 Protects Sector 164 from program or erase 4 1 read-write PROT165 Protects Sector 165 from program or erase 5 1 read-write PROT166 Protects Sector 166 from program or erase 6 1 read-write PROT167 Protects Sector 167 from program or erase 7 1 read-write PROT168 Protects Sector 168 from program or erase 8 1 read-write PROT169 Protects Sector 169 from program or erase 9 1 read-write PROT170 Protects Sector 170 from program or erase 10 1 read-write PROT171 Protects Sector 171 from program or erase 11 1 read-write PROT172 Protects Sector 172 from program or erase 12 1 read-write PROT173 Protects Sector 173 from program or erase 13 1 read-write PROT174 Protects Sector 174 from program or erase 14 1 read-write PROT175 Protects Sector 175 from program or erase 15 1 read-write PROT176 Protects Sector 176 from program or erase 16 1 read-write PROT177 Protects Sector 177 from program or erase 17 1 read-write PROT178 Protects Sector 178 from program or erase 18 1 read-write PROT179 Protects Sector 179 from program or erase 19 1 read-write PROT180 Protects Sector 180 from program or erase 20 1 read-write PROT181 Protects Sector 181 from program or erase 21 1 read-write PROT182 Protects Sector 182 from program or erase 22 1 read-write PROT183 Protects Sector 183 from program or erase 23 1 read-write PROT184 Protects Sector 184 from program or erase 24 1 read-write PROT185 Protects Sector 185 from program or erase 25 1 read-write PROT186 Protects Sector 186 from program or erase 26 1 read-write PROT187 Protects Sector 187 from program or erase 27 1 read-write PROT188 Protects Sector 188 from program or erase 28 1 read-write PROT189 Protects Sector 189 from program or erase 29 1 read-write PROT190 Protects Sector 190 from program or erase 30 1 read-write PROT191 Protects Sector 191 from program or erase 31 1 read-write FLCTL_BANK1_MAIN_WEPROT6 BANK1_MAIN_WEPROT6 Main Memory Bank1 Write/Erase Protection Register 6 0x258 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PROT192 Protects Sector 192 from program or erase 0 1 read-write PROT193 Protects Sector 193 from program or erase 1 1 read-write PROT194 Protects Sector 194 from program or erase 2 1 read-write PROT195 Protects Sector 195 from program or erase 3 1 read-write PROT196 Protects Sector 196 from program or erase 4 1 read-write PROT197 Protects Sector 197 from program or erase 5 1 read-write PROT198 Protects Sector 198 from program or erase 6 1 read-write PROT199 Protects Sector 199 from program or erase 7 1 read-write PROT200 Protects Sector 200 from program or erase 8 1 read-write PROT201 Protects Sector 201 from program or erase 9 1 read-write PROT202 Protects Sector 202 from program or erase 10 1 read-write PROT203 Protects Sector 203 from program or erase 11 1 read-write PROT204 Protects Sector 204 from program or erase 12 1 read-write PROT205 Protects Sector 205 from program or erase 13 1 read-write PROT206 Protects Sector 206 from program or erase 14 1 read-write PROT207 Protects Sector 207 from program or erase 15 1 read-write PROT208 Protects Sector 208 from program or erase 16 1 read-write PROT209 Protects Sector 209 from program or erase 17 1 read-write PROT210 Protects Sector 210 from program or erase 18 1 read-write PROT211 Protects Sector 211 from program or erase 19 1 read-write PROT212 Protects Sector 212 from program or erase 20 1 read-write PROT213 Protects Sector 213 from program or erase 21 1 read-write PROT214 Protects Sector 214 from program or erase 22 1 read-write PROT215 Protects Sector 215 from program or erase 23 1 read-write PROT216 Protects Sector 216 from program or erase 24 1 read-write PROT217 Protects Sector 217 from program or erase 25 1 read-write PROT218 Protects Sector 218 from program or erase 26 1 read-write PROT219 Protects Sector 219 from program or erase 27 1 read-write PROT220 Protects Sector 220 from program or erase 28 1 read-write PROT221 Protects Sector 221 from program or erase 29 1 read-write PROT222 Protects Sector 222 from program or erase 30 1 read-write PROT223 Protects Sector 223 from program or erase 31 1 read-write FLCTL_BANK1_MAIN_WEPROT7 BANK1_MAIN_WEPROT7 Main Memory Bank1 Write/Erase Protection Register 7 0x25C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PROT224 Protects Sector 224 from program or erase 0 1 read-write PROT225 Protects Sector 225 from program or erase 1 1 read-write PROT226 Protects Sector 226 from program or erase 2 1 read-write PROT227 Protects Sector 227 from program or erase 3 1 read-write PROT228 Protects Sector 228 from program or erase 4 1 read-write PROT229 Protects Sector 229 from program or erase 5 1 read-write PROT230 Protects Sector 230 from program or erase 6 1 read-write PROT231 Protects Sector 231 from program or erase 7 1 read-write PROT232 Protects Sector 232 from program or erase 8 1 read-write PROT233 Protects Sector 233 from program or erase 9 1 read-write PROT234 Protects Sector 234 from program or erase 10 1 read-write PROT235 Protects Sector 235 from program or erase 11 1 read-write PROT236 Protects Sector 236 from program or erase 12 1 read-write PROT237 Protects Sector 237 from program or erase 13 1 read-write PROT238 Protects Sector 238 from program or erase 14 1 read-write PROT239 Protects Sector 239 from program or erase 15 1 read-write PROT240 Protects Sector 240 from program or erase 16 1 read-write PROT241 Protects Sector 241 from program or erase 17 1 read-write PROT242 Protects Sector 242 from program or erase 18 1 read-write PROT243 Protects Sector 243 from program or erase 19 1 read-write PROT244 Protects Sector 244 from program or erase 20 1 read-write PROT245 Protects Sector 245 from program or erase 21 1 read-write PROT246 Protects Sector 246 from program or erase 22 1 read-write PROT247 Protects Sector 247 from program or erase 23 1 read-write PROT248 Protects Sector 248 from program or erase 24 1 read-write PROT249 Protects Sector 249 from program or erase 25 1 read-write PROT250 Protects Sector 250 from program or erase 26 1 read-write PROT251 Protects Sector 251 from program or erase 27 1 read-write PROT252 Protects Sector 252 from program or erase 28 1 read-write PROT253 Protects Sector 253 from program or erase 29 1 read-write PROT254 Protects Sector 254 from program or erase 30 1 read-write PROT255 Protects Sector 255 from program or erase 31 1 read-write FLCTL_BANK1_RDCTL BANK1_RDCTL Bank1 Read Control Register 0x14 32 read-write n 0x0 0xFFFFFFFF BUFD Enables read buffering feature for data reads to this Bank 5 1 read-write BUFI Enables read buffering feature for instruction fetches to this Bank 4 1 read-write RD_MODE Flash read mode control setting for Bank 0 0 4 read-write RD_MODE_0 Normal read mode 0 RD_MODE_1 Read Margin 0 1 RD_MODE_10 Read Margin 1B 10 RD_MODE_2 Read Margin 1 2 RD_MODE_3 Program Verify 3 RD_MODE_4 Erase Verify 4 RD_MODE_5 Leakage Verify 5 RD_MODE_9 Read Margin 0B 9 RD_MODE_STATUS Read mode 16 4 read-only RD_MODE_STATUS_0 Normal read mode 0 RD_MODE_STATUS_1 Read Margin 0 1 RD_MODE_STATUS_10 Read Margin 1B 10 RD_MODE_STATUS_2 Read Margin 1 2 RD_MODE_STATUS_3 Program Verify 3 RD_MODE_STATUS_4 Erase Verify 4 RD_MODE_STATUS_5 Leakage Verify 5 RD_MODE_STATUS_9 Read Margin 0B 9 WAIT Number of wait states for read 12 4 read-write WAIT_0 0 wait states 0 WAIT_1 1 wait states 1 WAIT_10 10 wait states 10 WAIT_11 11 wait states 11 WAIT_12 12 wait states 12 WAIT_13 13 wait states 13 WAIT_14 14 wait states 14 WAIT_15 15 wait states 15 WAIT_2 2 wait states 2 WAIT_3 3 wait states 3 WAIT_4 4 wait states 4 WAIT_5 5 wait states 5 WAIT_6 6 wait states 6 WAIT_7 7 wait states 7 WAIT_8 8 wait states 8 WAIT_9 9 wait states 9 FLCTL_BMRK_CMP BMRK_CMP Benchmark Count Compare Register 0xDC 32 read-write n 0x10000 0xFFFFFFFF COUNT Reflects the threshold value that is compared against either the IFETCH or DREAD Benchmark Counters 0 32 read-write FLCTL_BMRK_CTLSTAT BMRK_CTLSTAT Benchmark Control and Status Register 0xD0 32 read-write n 0x0 0xFFFFFFFF CMP_EN When 1, enables comparison of the Instruction or Data Benchmark Registers against the threshold value 2 1 read-write CMP_SEL Selects which benchmark register should be compared against the threshold 3 1 read-write en_1_0x0 Compares the Instruction Benchmark Register against the threshold value 0 en_2_0x1 Compares the Data Benchmark Register against the threshold value 1 D_BMRK When 1, increments the Data Benchmark count register on each data read access to the Flash 1 1 read-write I_BMRK When 1, increments the Instruction Benchmark count register on each instruction fetch to the Flash 0 1 read-write FLCTL_BMRK_DREAD BMRK_DREAD Benchmark Data Read Count Register 0xD8 32 read-write n 0x0 0xFFFFFFFF COUNT Reflects the number of Data Read operations to the Flash (increments by one on each read) 0 32 read-write FLCTL_BMRK_IFETCH BMRK_IFETCH Benchmark Instruction Fetch Count Register 0xD4 32 read-write n 0x0 0xFFFFFFFF COUNT Reflects the number of Instruction Fetches to the Flash (increments by one on each fetch) 0 32 read-write FLCTL_BURSTPRG_TIMCTL BURSTPRG_TIMCTL Burst Program Timing Control Register 0x120 32 read-only n 0x0 0x0 ACTIVE Length of the Active phase for this operation 8 20 read-only FLCTL_CLRIFG CLRIFG Clear Interrupt Flag Register 0xF8 32 read-write n 0x0 0xFFFFFFFF AVPRE Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 1 1 write-only AVPST Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 2 1 write-only BMRK Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 8 1 write-only ERASE Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 5 1 write-only PRG Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 3 1 write-only PRGB Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 4 1 write-only PRG_ERR Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 9 1 write-only RDBRST Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 0 1 write-only FLCTL_ERASE_CTLSTAT ERASE_CTLSTAT Erase Control and Status Register 0xA0 32 read-write n 0x0 0xFFFFFFFF ADDR_ERR Erase Operation was terminated due to attempted erase of reserved memory address 18 1 read-only CLR_STAT Clear status bits 18-16 of this register 19 1 write-only MODE Erase mode selected by application 1 1 read-write MODE_0 Sector Erase (controlled by FLTCTL_ERASE_SECTADDR) 0 MODE_1 Mass Erase (includes all Main and Information memory sectors that don't have corresponding WE bits set) 1 START Start of Erase operation 0 1 write-only STATUS Status of erase operations in the Flash memory 16 2 read-only STATUS_0 Idle (no program operation currently active) 0 STATUS_1 Erase operation triggered to START but pending 1 STATUS_2 Erase operation in progress 2 STATUS_3 Erase operation completed (status of completed erase remains in this state unless explicitly cleared by SW) 3 TYPE Type of memory that erase operation is carried out on 2 2 read-write TYPE_0 Main Memory 0 TYPE_1 Information Memory 1 TYPE_3 Engineering Memory 3 FLCTL_ERASE_SECTADDR ERASE_SECTADDR Erase Sector Address Register 0xA4 32 read-write n 0x0 0xFFFFFFFF SECT_ADDRESS Address of Sector being Erased 0 22 read-write FLCTL_ERASE_TIMCTL ERASE_TIMCTL Erase Timing Control Register 0x118 32 read-only n 0x0 0x0 ACTIVE Length of the Active phase for this operation 8 20 read-only HOLD Length of the Hold phase for this operation 28 4 read-only SETUP Length of the Setup phase for this operation 0 8 read-only FLCTL_ERSVER_TIMCTL ERSVER_TIMCTL Erase Verify Timing Control Register 0x10C 32 read-only n 0x0 0x0 SETUP Length of the Setup phase for this operation 0 8 read-only FLCTL_IE IE Interrupt Enable Register 0xF4 32 read-write n 0x0 0xFFFFFFFF AVPRE If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG 1 1 read-write AVPST If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG 2 1 read-write BMRK If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG 8 1 read-write ERASE If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG 5 1 read-write PRG If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG 3 1 read-write PRGB If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG 4 1 read-write PRG_ERR If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG 9 1 read-write RDBRST If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG 0 1 read-write FLCTL_IFG IFG Interrupt Flag Register 0xF0 32 read-write n 0x0 0xFFFFFFFF AVPRE If set to 1, indicates that the pre-program verify operation has detected an error 1 1 read-only AVPST If set to 1, indicates that the post-program verify operation has failed comparison 2 1 read-only BMRK If set to 1, indicates that a Benchmark Compare match occurred 8 1 read-only ERASE If set to 1, indicates that the Erase operation is complete 5 1 read-only PRG If set to 1, indicates that a word Program operation is complete 3 1 read-only PRGB If set to 1, indicates that the configured Burst Program operation is complete 4 1 read-only PRG_ERR If set to 1, indicates a word composition error in full word write mode (possible data loss due to writes crossing over to a new 128bit boundary before full word has been composed) 9 1 read-only RDBRST If set to 1, indicates that the Read Burst/Compare operation is complete 0 1 read-only FLCTL_LKGVER_TIMCTL LKGVER_TIMCTL Leakage Verify Timing Control Register 0x110 32 read-only n 0x0 0x0 SETUP Length of the Setup phase for this operation 0 8 read-only FLCTL_MASSERASE_TIMCTL MASSERASE_TIMCTL Mass Erase Timing Control Register 0x11C 32 read-only n 0x0 0x0 BOOST_ACTIVE Length of the time for which LDO Boost Signal is kept active 0 8 read-only BOOST_HOLD Length for which Flash deactivates the LDO Boost signal before processing any new commands 8 8 read-only FLCTL_POWER_STAT POWER_STAT Power Status Register 0x0 32 read-only n 0x80 0xFFFFFFFF IREFSTAT PSS IREF stable status 5 1 read-only IREFSTAT_0 IREF not stable 0 IREFSTAT_1 IREF stable 1 LDOSTAT PSS FLDO GOOD status 3 1 read-only LDOSTAT_0 FLDO not GOOD 0 LDOSTAT_1 FLDO GOOD 1 PSTAT Flash power status 0 3 read-only PSTAT_0 Flash IP in power-down mode 0 PSTAT_1 Flash IP Vdd domain power-up in progress 1 PSTAT_2 PSS LDO_GOOD, IREF_OK and VREF_OK check in progress 2 PSTAT_3 Flash IP SAFE_LV check in progress 3 PSTAT_4 Flash IP Active 4 PSTAT_5 Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. 5 PSTAT_6 Flash IP in Standby mode 6 PSTAT_7 Flash IP in Current mirror boost state 7 RD_2T Indicates if Flash is being accessed in 2T mode 7 1 read-only RD_2T_0 Flash reads are in 1T mode 0 RD_2T_1 Flash reads are in 2T mode 1 TRIMSTAT PSS trim done status 6 1 read-only TRIMSTAT_0 PSS trim not complete 0 TRIMSTAT_1 PSS trim complete 1 VREFSTAT PSS VREF stable status 4 1 read-only VREFSTAT_0 Flash LDO not stable 0 VREFSTAT_1 Flash LDO stable 1 FLCTL_PRGBRST_CTLSTAT PRGBRST_CTLSTAT Program Burst Control and Status Register 0x54 32 read-write n 0xC0 0xFFFFFFFF ADDR_ERR Burst Operation was terminated due to attempted program of reserved memory 21 1 read-only AUTO_PRE Auto-Verify operation before the Burst Program 6 1 read-write AUTO_PRE_0 No program verify operations carried out 0 AUTO_PRE_1 Causes an automatic Burst Program Verify after the Burst Program Operation 1 AUTO_PST Auto-Verify operation after the Burst Program 7 1 read-write AUTO_PST_0 No program verify operations carried out 0 AUTO_PST_1 Causes an automatic Burst Program Verify before the Burst Program Operation 1 BURST_STATUS Status of a Burst Operation 16 3 read-only BURST_STATUS_0 Idle (Burst not active) 0 BURST_STATUS_1 Burst program started but pending 1 BURST_STATUS_2 Burst active, with 1st 128 bit word being written into Flash 2 BURST_STATUS_3 Burst active, with 2nd 128 bit word being written into Flash 3 BURST_STATUS_4 Burst active, with 3rd 128 bit word being written into Flash 4 BURST_STATUS_5 Burst active, with 4th 128 bit word being written into Flash 5 BURST_STATUS_7 Burst Complete (status of completed burst remains in this state unless explicitly cleared by SW) 7 CLR_STAT Clear status bits 21-16 of this register 23 1 write-only LEN Length of burst 3 3 read-write LEN_0 No burst operation 0 LEN_1 1 word burst of 128 bits, starting with address in the FLCTL_PRGBRST_STARTADDR Register 1 LEN_2 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register 2 LEN_3 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register 3 LEN_4 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register 4 PRE_ERR Burst Operation encountered preprogram auto-verify errors 19 1 read-only PST_ERR Burst Operation encountered postprogram auto-verify errors 20 1 read-only START Trigger start of burst program operation 0 1 write-only TYPE Type of memory that burst program is carried out on 1 2 read-write TYPE_0 Main Memory 0 TYPE_1 Information Memory 1 TYPE_3 Engineering Memory 3 FLCTL_PRGBRST_DATA0_0 PRGBRST_DATA0_0 Program Burst Data0 Register0 0x60 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DATAIN Program Burst 128 bit Data Word 0 0 32 read-write FLCTL_PRGBRST_DATA0_1 PRGBRST_DATA0_1 Program Burst Data0 Register1 0x64 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DATAIN Program Burst 128 bit Data Word 0 0 32 read-write FLCTL_PRGBRST_DATA0_2 PRGBRST_DATA0_2 Program Burst Data0 Register2 0x68 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DATAIN Program Burst 128 bit Data Word 0 0 32 read-write FLCTL_PRGBRST_DATA0_3 PRGBRST_DATA0_3 Program Burst Data0 Register3 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DATAIN Program Burst 128 bit Data Word 0 0 32 read-write FLCTL_PRGBRST_DATA1_0 PRGBRST_DATA1_0 Program Burst Data1 Register0 0x70 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DATAIN Program Burst 128 bit Data Word 1 0 32 read-write FLCTL_PRGBRST_DATA1_1 PRGBRST_DATA1_1 Program Burst Data1 Register1 0x74 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DATAIN Program Burst 128 bit Data Word 1 0 32 read-write FLCTL_PRGBRST_DATA1_2 PRGBRST_DATA1_2 Program Burst Data1 Register2 0x78 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DATAIN Program Burst 128 bit Data Word 1 0 32 read-write FLCTL_PRGBRST_DATA1_3 PRGBRST_DATA1_3 Program Burst Data1 Register3 0x7C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DATAIN Program Burst 128 bit Data Word 1 0 32 read-write FLCTL_PRGBRST_DATA2_0 PRGBRST_DATA2_0 Program Burst Data2 Register0 0x80 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DATAIN Program Burst 128 bit Data Word 2 0 32 read-write FLCTL_PRGBRST_DATA2_1 PRGBRST_DATA2_1 Program Burst Data2 Register1 0x84 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DATAIN Program Burst 128 bit Data Word 2 0 32 read-write FLCTL_PRGBRST_DATA2_2 PRGBRST_DATA2_2 Program Burst Data2 Register2 0x88 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DATAIN Program Burst 128 bit Data Word 2 0 32 read-write FLCTL_PRGBRST_DATA2_3 PRGBRST_DATA2_3 Program Burst Data2 Register3 0x8C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DATAIN Program Burst 128 bit Data Word 2 0 32 read-write FLCTL_PRGBRST_DATA3_0 PRGBRST_DATA3_0 Program Burst Data3 Register0 0x90 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DATAIN Program Burst 128 bit Data Word 3 0 32 read-write FLCTL_PRGBRST_DATA3_1 PRGBRST_DATA3_1 Program Burst Data3 Register1 0x94 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DATAIN Program Burst 128 bit Data Word 3 0 32 read-write FLCTL_PRGBRST_DATA3_2 PRGBRST_DATA3_2 Program Burst Data3 Register2 0x98 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DATAIN Program Burst 128 bit Data Word 3 0 32 read-write FLCTL_PRGBRST_DATA3_3 PRGBRST_DATA3_3 Program Burst Data3 Register3 0x9C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DATAIN Program Burst 128 bit Data Word 3 0 32 read-write FLCTL_PRGBRST_STARTADDR PRGBRST_STARTADDR Program Burst Start Address Register 0x58 32 read-write n 0x0 0xFFFFFFFF START_ADDRESS Start Address of Program Burst Operation 0 22 read-write FLCTL_PRGVER_TIMCTL PRGVER_TIMCTL Program Verify Timing Control Register 0x108 32 read-only n 0x0 0x0 ACTIVE Length of the Active phase for this operation 8 4 read-only HOLD Length of the Hold phase for this operation 12 4 read-only SETUP Length of the Setup phase for this operation 0 8 read-only FLCTL_PRG_CTLSTAT PRG_CTLSTAT Program Control and Status Register 0x50 32 read-write n 0xC 0xFFFFFFFF BNK_ACT Bank active 18 1 read-only BNK_ACT_0 Word in Bank0 being programmed 0 BNK_ACT_1 Word in Bank1 being programmed 1 ENABLE Master control for all word program operations 0 1 read-write ENABLE_0 Word program operation disabled 0 ENABLE_1 Word program operation enabled 1 MODE Write mode 1 1 read-write MODE_0 Write immediate mode. Starts program operation immediately on each write to the Flash 0 MODE_1 Full word write mode. Flash controller collates data over multiple writes to compose the full 128bit word before initiating the program operation 1 STATUS Status of program operations in the Flash memory 16 2 read-only STATUS_0 Idle (no program operation currently active) 0 STATUS_1 Single word program operation triggered, but pending 1 STATUS_2 Single word program in progress 2 VER_PRE Controls automatic pre program verify operations 2 1 read-write VER_PRE_0 No pre program verification 0 VER_PRE_1 Pre verify feature automatically invoked for each write operation (irrespective of the mode) 1 VER_PST Controls automatic post program verify operations 3 1 read-write VER_PST_0 No post program verification 0 VER_PST_1 Post verify feature automatically invoked for each write operation (irrespective of the mode) 1 FLCTL_PROGRAM_TIMCTL PROGRAM_TIMCTL Program Timing Control Register 0x114 32 read-only n 0x0 0x0 ACTIVE Length of the Active phase for this operation 8 20 read-only HOLD Length of the Hold phase for this operation 28 4 read-only SETUP Length of the Setup phase for this operation 0 8 read-only FLCTL_RDBRST_CTLSTAT RDBRST_CTLSTAT Read Burst/Compare Control and Status Register 0x20 32 read-write n 0x0 0xFFFFFFFF ADDR_ERR Burst/Compare Operation was terminated due to access to 19 1 read-only BRST_STAT Status of Burst/Compare operation 16 2 read-only BRST_STAT_0 Idle 0 BRST_STAT_1 Burst/Compare START bit written, but operation pending 1 BRST_STAT_2 Burst/Compare in progress 2 BRST_STAT_3 Burst complete (status of completed burst remains in this state unless explicitly cleared by SW) 3 CLR_STAT Clear status bits 19-16 of this register 23 1 write-only CMP_ERR Burst/Compare Operation encountered atleast one data 18 1 read-only DATA_CMP Data pattern used for comparison against memory read data 4 1 read-write DATA_CMP_0 0000_0000_0000_0000_0000_0000_0000_0000 0 DATA_CMP_1 FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF 1 MEM_TYPE Type of memory that burst is carried out on 1 2 read-write MEM_TYPE_0 Main Memory 0 MEM_TYPE_1 Information Memory 1 MEM_TYPE_3 Engineering Memory 3 START Start of burst/compare operation 0 1 write-only STOP_FAIL Terminate burst/compare operation 3 1 read-write TEST_EN Enable comparison against test data compare registers 6 1 read-write FLCTL_RDBRST_FAILADDR RDBRST_FAILADDR Read Burst/Compare Fail Address Register 0x3C 32 read-write n 0x0 0xFFFFFFFF FAIL_ADDRESS Reflects address of last failed compare 0 21 read-write FLCTL_RDBRST_FAILCNT RDBRST_FAILCNT Read Burst/Compare Fail Count Register 0x40 32 read-write n 0x0 0xFFFFFFFF FAIL_COUNT Number of failures encountered in burst operation 0 17 read-write FLCTL_RDBRST_LEN RDBRST_LEN Read Burst/Compare Length Register 0x28 32 read-write n 0x0 0xFFFFFFFF BURST_LENGTH Length of Burst Operation 0 21 read-write FLCTL_RDBRST_STARTADDR RDBRST_STARTADDR Read Burst/Compare Start Address Register 0x24 32 read-write n 0x0 0xFFFFFFFF START_ADDRESS Start Address of Burst Operation 0 21 read-write FLCTL_READMARGIN_TIMCTL READMARGIN_TIMCTL Read Margin Timing Control Register 0x104 32 read-only n 0x0 0x0 SETUP Length of the Setup phase for this operation 0 8 read-only FLCTL_READ_TIMCTL READ_TIMCTL Read Timing Control Register 0x100 32 read-only n 0x0 0x0 IREF_BOOST1 Length of the IREF_BOOST1 signal of the IP 12 4 read-only SETUP Configures the length of the Setup phase for this operation 0 8 read-only SETUP_LONG Length of the Setup time into read mode when the device is recovering from one of the following conditions: Moving from Power-down or Standby back to Active and device is not trimmed. Moving from standby to active state in low-frequency active mode. Recovering from the LDO Boost operation after a Mass Erase. 16 8 read-only FLCTL_SETIFG SETIFG Set Interrupt Flag Register 0xFC 32 read-write n 0x0 0xFFFFFFFF AVPRE Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 1 1 write-only AVPST Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 2 1 write-only BMRK Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 8 1 write-only ERASE Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 5 1 write-only PRG Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 3 1 write-only PRGB Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 4 1 write-only PRG_ERR Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 9 1 write-only RDBRST Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 0 1 write-only FPB FPB FPB 0xE0002000 0x0 0x1000 registers n FP_COMP0 FP_COMP0 Flash Patch Comparator Registers 0x8 32 read-write n 0x0 0x1 COMP Comparison address. 2 27 read-write ENABLE Compare and remap enable for Flash Patch Comparator Register 0. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit. 0 1 read-write en_0b0 Flash Patch Comparator Register 0 compare and remap disabled 0 en_0b1 Flash Patch Comparator Register 0 compare and remap enabled 1 REPLACE This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting. 30 2 read-write en_0b00 remap to remap address. See FP_REMAP 0 en_0b01 set BKPT on lower halfword, upper is unaffected 1 en_0b10 set BKPT on upper halfword, lower is unaffected 2 en_0b11 set BKPT on both lower and upper halfwords. 3 FP_COMP1 FP_COMP1 Flash Patch Comparator Registers 0xC 32 read-write n 0x0 0x1 COMP Comparison address. 2 27 read-write ENABLE Compare and remap enable for Flash Patch Comparator Register 1. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit. 0 1 read-write en_0b0 Flash Patch Comparator Register 1 compare and remap disabled 0 en_0b1 Flash Patch Comparator Register 1 compare and remap enabled 1 REPLACE This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting. 30 2 read-write en_0b00 remap to remap address. See FP_REMAP 0 en_0b01 set BKPT on lower halfword, upper is unaffected 1 en_0b10 set BKPT on upper halfword, lower is unaffected 2 en_0b11 set BKPT on both lower and upper halfwords. 3 FP_COMP2 FP_COMP2 Flash Patch Comparator Registers 0x10 32 read-write n 0x0 0x1 COMP Comparison address. 2 27 read-write ENABLE Compare and remap enable for Flash Patch Comparator Register 2. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit. 0 1 read-write en_0b0 Flash Patch Comparator Register 2 compare and remap disabled 0 en_0b1 Flash Patch Comparator Register 2 compare and remap enabled 1 REPLACE This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting. 30 2 read-write en_0b00 remap to remap address. See FP_REMAP 0 en_0b01 set BKPT on lower halfword, upper is unaffected 1 en_0b10 set BKPT on upper halfword, lower is unaffected 2 en_0b11 set BKPT on both lower and upper halfwords. 3 FP_COMP3 FP_COMP3 Flash Patch Comparator Registers 0x14 32 read-write n 0x0 0x1 COMP Comparison address. 2 27 read-write ENABLE Compare and remap enable for Flash Patch Comparator Register 3. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit. 0 1 read-write en_0b0 Flash Patch Comparator Register 3 compare and remap disabled 0 en_0b1 Flash Patch Comparator Register 3 compare and remap enabled 1 REPLACE This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting. 30 2 read-write en_0b00 remap to remap address. See FP_REMAP 0 en_0b01 set BKPT on lower halfword, upper is unaffected 1 en_0b10 set BKPT on upper halfword, lower is unaffected 2 en_0b11 set BKPT on both lower and upper halfwords. 3 FP_COMP4 FP_COMP4 Flash Patch Comparator Registers 0x18 32 read-write n 0x0 0x1 COMP Comparison address. 2 27 read-write ENABLE Compare and remap enable for Flash Patch Comparator Register 4. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit. 0 1 read-write en_0b0 Flash Patch Comparator Register 4 compare and remap disabled 0 en_0b1 Flash Patch Comparator Register 4 compare and remap enabled 1 REPLACE This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting. 30 2 read-write en_0b00 remap to remap address. See FP_REMAP 0 en_0b01 set BKPT on lower halfword, upper is unaffected 1 en_0b10 set BKPT on upper halfword, lower is unaffected 2 en_0b11 set BKPT on both lower and upper halfwords. 3 FP_COMP5 FP_COMP5 Flash Patch Comparator Registers 0x1C 32 read-write n 0x0 0x1 COMP Comparison address. 2 27 read-write ENABLE Compare and remap enable for Flash Patch Comparator Register 5. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit. 0 1 read-write en_0b0 Flash Patch Comparator Register 5 compare and remap disabled 0 en_0b1 Flash Patch Comparator Register 5 compare and remap enabled 1 REPLACE This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting. 30 2 read-write en_0b00 remap to remap address. See FP_REMAP 0 en_0b01 set BKPT on lower halfword, upper is unaffected 1 en_0b10 set BKPT on upper halfword, lower is unaffected 2 en_0b11 set BKPT on both lower and upper halfwords. 3 FP_COMP6 FP_COMP6 Flash Patch Comparator Registers 0x20 32 read-write n 0x0 0x1 COMP Comparison address. 2 27 read-write ENABLE Compare and remap enable for Flash Patch Comparator Register 6. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit. 0 1 read-write en_0b0 Flash Patch Comparator Register 6 compare and remap disabled 0 en_0b1 Flash Patch Comparator Register 6 compare and remap enabled 1 REPLACE This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting. 30 2 read-write en_0b00 remap to remap address. See FP_REMAP 0 en_0b01 set BKPT on lower halfword, upper is unaffected 1 en_0b10 set BKPT on upper halfword, lower is unaffected 2 en_0b11 set BKPT on both lower and upper halfwords. 3 FP_COMP7 FP_COMP7 Flash Patch Comparator Registers 0x24 32 read-write n 0x0 0x1 COMP Comparison address. 2 27 read-write ENABLE Compare and remap enable for Flash Patch Comparator Register 7. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit. 0 1 read-write en_0b0 Flash Patch Comparator Register 7 compare and remap disabled 0 en_0b1 Flash Patch Comparator Register 7 compare and remap enabled 1 REPLACE This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting. 30 2 read-write en_0b00 remap to remap address. See FP_REMAP 0 en_0b01 set BKPT on lower halfword, upper is unaffected 1 en_0b10 set BKPT on upper halfword, lower is unaffected 2 en_0b11 set BKPT on both lower and upper halfwords. 3 FP_CTRL FP_CTRL Flash Patch Control Register 0x0 32 read-write n 0x130 0x0 ENABLE Flash patch unit enable bit 0 1 read-write en_0b0 flash patch unit disabled 0 en_0b1 flash patch unit enabled 1 KEY Key field. To write to the Flash Patch Control Register, you must write a 1 to this write-only bit. 1 1 write-only NUM_CODE1 Number of code slots field. 4 4 read-only en_0b0000 no code slots 0 en_0b0010 two code slots 2 en_0b0110 six code slots 6 NUM_CODE2 Number of full banks of code comparators, sixteen comparators per bank. Where less than sixteen code comparators are provided, the bank count is zero, and the number present indicated by NUM_CODE. This read only field contains 3'b000 to indicate 0 banks for Cortex-M4 processor. 12 2 read-only NUM_LIT Number of literal slots field. 8 4 read-only en_0b0000 no literal slots 0 en_0b0010 two literal slots 2 FP_REMAP FP_REMAP Flash Patch Remap Register 0x4 32 read-write n 0x0 0x0 REMAP Remap base address field. 5 24 read-write ITM ITM ITM 0xE0000000 0x0 0x1000 registers n IMCR IMCR ITM Integration Mode Control Register 0xF00 32 read-write n 0x0 0x0 INTEGRATION 0 1 read-write en_0b0 ATVALIDM normal 0 en_0b1 ATVALIDM driven from Integration Write Register 1 IWR IWR ITM Integration Write Register 0xEF8 32 write-only n 0x0 0x0 ATVALIDM When the integration mode is set: 0 = ATVALIDM clear. 1 = ATVALIDM set. 0 1 write-only en_0b0 ATVALIDM clear 0 en_0b1 ATVALIDM set 1 LAR LAR ITM Lock Access Register 0xFB0 32 write-only n 0x0 0x0 LOCK_ACCESS A privileged write of 0xC5ACCE55 enables more write access to Control Register 0xE00::0xFFC. An invalid write removes write access. 0 32 write-only LSR LSR ITM Lock Status Register 0xFB4 32 read-only n 0x3 0x0 ACCESS Write access to component is blocked. All writes are ignored, reads are permitted. 1 1 read-only BYTEACC You cannot implement 8-bit lock accesses. 2 1 read-only PRESENT Indicates that a lock mechanism exists for this component. 0 1 read-only STIM0 STIM0 ITM Stimulus Port 0 0x0 32 read-write n 0x0 0x0 STIM1 STIM1 ITM Stimulus Port 1 0x4 32 read-write n 0x0 0x0 STIM10 STIM10 ITM Stimulus Port 10 0x28 32 read-write n 0x0 0x0 STIM11 STIM11 ITM Stimulus Port 11 0x2C 32 read-write n 0x0 0x0 STIM12 STIM12 ITM Stimulus Port 12 0x30 32 read-write n 0x0 0x0 STIM13 STIM13 ITM Stimulus Port 13 0x34 32 read-write n 0x0 0x0 STIM14 STIM14 ITM Stimulus Port 14 0x38 32 read-write n 0x0 0x0 STIM15 STIM15 ITM Stimulus Port 15 0x3C 32 read-write n 0x0 0x0 STIM16 STIM16 ITM Stimulus Port 16 0x40 32 read-write n 0x0 0x0 STIM17 STIM17 ITM Stimulus Port 17 0x44 32 read-write n 0x0 0x0 STIM18 STIM18 ITM Stimulus Port 18 0x48 32 read-write n 0x0 0x0 STIM19 STIM19 ITM Stimulus Port 19 0x4C 32 read-write n 0x0 0x0 STIM2 STIM2 ITM Stimulus Port 2 0x8 32 read-write n 0x0 0x0 STIM20 STIM20 ITM Stimulus Port 20 0x50 32 read-write n 0x0 0x0 STIM21 STIM21 ITM Stimulus Port 21 0x54 32 read-write n 0x0 0x0 STIM22 STIM22 ITM Stimulus Port 22 0x58 32 read-write n 0x0 0x0 STIM23 STIM23 ITM Stimulus Port 23 0x5C 32 read-write n 0x0 0x0 STIM24 STIM24 ITM Stimulus Port 24 0x60 32 read-write n 0x0 0x0 STIM25 STIM25 ITM Stimulus Port 25 0x64 32 read-write n 0x0 0x0 STIM26 STIM26 ITM Stimulus Port 26 0x68 32 read-write n 0x0 0x0 STIM27 STIM27 ITM Stimulus Port 27 0x6C 32 read-write n 0x0 0x0 STIM28 STIM28 ITM Stimulus Port 28 0x70 32 read-write n 0x0 0x0 STIM29 STIM29 ITM Stimulus Port 29 0x74 32 read-write n 0x0 0x0 STIM3 STIM3 ITM Stimulus Port 3 0xC 32 read-write n 0x0 0x0 STIM30 STIM30 ITM Stimulus Port 30 0x78 32 read-write n 0x0 0x0 STIM31 STIM31 ITM Stimulus Port 31 0x7C 32 read-write n 0x0 0x0 STIM4 STIM4 ITM Stimulus Port 4 0x10 32 read-write n 0x0 0x0 STIM5 STIM5 ITM Stimulus Port 5 0x14 32 read-write n 0x0 0x0 STIM6 STIM6 ITM Stimulus Port 6 0x18 32 read-write n 0x0 0x0 STIM7 STIM7 ITM Stimulus Port 7 0x1C 32 read-write n 0x0 0x0 STIM8 STIM8 ITM Stimulus Port 8 0x20 32 read-write n 0x0 0x0 STIM9 STIM9 ITM Stimulus Port 9 0x24 32 read-write n 0x0 0x0 TCR TCR ITM Trace Control Register 0xE80 32 read-write n 0x0 0x0 ATBID ATB ID for CoreSight system. 16 7 read-write BUSY Set when ITM events present and being drained. 23 1 read-write DWTENA Enables the DWT stimulus. 3 1 read-write ITMENA Enable ITM. This is the master enable, and must be set before ITM Stimulus and Trace Enable registers can be written. 0 1 read-write SWOENA Enables asynchronous clocking of the timestamp counter. 4 1 read-write SYNCENA Enables sync packets for TPIU. 2 1 read-write TSENA Enables differential timestamps. Differential timestamps are emitted when a packet is written to the FIFO with a non-zero timestamp counter, and when the timestamp counter overflows. Timestamps are emitted during idle times after a fixed number of two million cycles. This provides a time reference for packets and inter-packet gaps. If SWOENA (bit [4]) is set, timestamps are triggered by activity on the internal trace bus only. In this case there is no regular timestamp output when the ITM is idle. 1 1 read-write TSPRESCALE TSPrescale Timestamp prescaler. 8 2 read-write en_0b00 no prescaling 0 en_0b01 divide by 4 1 en_0b10 divide by 16 2 en_0b11 divide by 64 3 TER TER ITM Trace Enable Register 0xE00 32 read-write n 0x0 0x0 STIMENA Bit mask to enable tracing on ITM stimulus ports. One bit per stimulus port. 0 32 read-write TPR TPR ITM Trace Privilege Register 0xE40 32 read-write n 0x0 0x0 PRIVMASK Bit mask to enable tracing on ITM stimulus ports: bit [0] = stimulus ports [7:0], bit [1] = stimulus ports [15:8], bit [2] = stimulus ports [23:16], bit [3] = stimulus ports [31:24]. 0 4 read-write PCM PCM PCM 0x40010000 0x0 0x14 registers n PCM_IRQ PCM Interrupt 2 PCMCLRIFG CLRIFG Clear Interrupt Flag Register 0x10 32 write-only n 0x0 0xFFFFFFFF CLR_AM_INVALID_TR_IFG Clear active mode invalid transition flag 2 1 write-only CLR_DCDC_ERROR_IFG Clear DC-DC error flag 6 1 write-only CLR_LPM_INVALID_CLK_IFG Clear LPM invalid clock flag 1 1 write-only CLR_LPM_INVALID_TR_IFG Clear LPM invalid transition flag 0 1 write-only PCMCTL0 CTL0 Control 0 Register 0x0 32 read-write n 0xA5960000 0xFFFFFFFF AMR Active Mode Request 0 4 read-write AMR_0 LDO based Active Mode at Core voltage setting 0. 0 AMR_1 LDO based Active Mode at Core voltage setting 1. 1 AMR_4 DC-DC based Active Mode at Core voltage setting 0. 4 AMR_5 DC-DC based Active Mode at Core voltage setting 1. 5 AMR_8 Low-Frequency Active Mode at Core voltage setting 0. 8 AMR_9 Low-Frequency Active Mode at Core voltage setting 1. 9 CPM Current Power Mode 8 6 read-only CPM_enum_read read CPM_0 LDO based Active Mode at Core voltage setting 0. 0 CPM_1 LDO based Active Mode at Core voltage setting 1. 1 CPM_16 LDO based LPM0 at Core voltage setting 0. 16 CPM_17 LDO based LPM0 at Core voltage setting 1. 17 CPM_20 DC-DC based LPM0 at Core voltage setting 0. 20 CPM_21 DC-DC based LPM0 at Core voltage setting 1. 21 CPM_24 Low-Frequency LPM0 at Core voltage setting 0. 24 CPM_25 Low-Frequency LPM0 at Core voltage setting 1. 25 CPM_32 LPM3 32 CPM_4 DC-DC based Active Mode at Core voltage setting 0. 4 CPM_5 DC-DC based Active Mode at Core voltage setting 1. 5 CPM_8 Low-Frequency Active Mode at Core voltage setting 0. 8 CPM_9 Low-Frequency Active Mode at Core voltage setting 1. 9 LPMR Low Power Mode Request 4 4 read-write LPMR_0 LPM3. Core voltage setting is similar to the mode from which LPM3 is entered. 0 LPMR_10 LPM3.5. Core voltage setting 0. 10 LPMR_12 LPM4.5 12 PCMKEY PCM key 16 16 read-write PCMCTL1 CTL1 Control 1 Register 0x4 32 read-write n 0xA5960000 0xFFFFFFFF FORCE_LPM_ENTRY Force LPM entry 2 1 read-write FORCE_LPM_ENTRY_0 PCM aborts LPM3/LPMx.5 transition if the active clock configuration does not meet the LPM3/LPMx.5 entry criteria. PCM generates the LPM_INVALID_CLK flag on abort to LPM3/LPMx.5 entry. 0 FORCE_LPM_ENTRY_1 PCM enters LPM3/LPMx.5 after shuting off the clocks forcefully. Application needs to ensure RTC and WDT are clocked using BCLK tree to keep these modules alive in LPM3/LPM3.5. In LPM4.5 all clocks are forcefully shutoff and the core voltage is turned off. 1 LOCKBKUP Lock Backup 1 1 read-write LOCKBKUP_0 Backup domain configuration defaults to reset condition 0 LOCKBKUP_1 Backup domain configuration remains locked during LPM3.5 entry and exit 1 LOCKLPM5 Lock LPM5 0 1 read-write LOCKLPM5_0 LPMx.5 configuration defaults to reset condition 0 LOCKLPM5_1 LPMx.5 configuration remains locked during LPMx.5 entry and exit 1 PCMKEY PCM key 16 16 read-write PMR_BUSY Power mode request busy flag 8 1 read-write PCMIE IE Interrupt Enable Register 0x8 32 read-write n 0x0 0xFFFFFFFF AM_INVALID_TR_IE Active mode invalid transition interrupt enable 2 1 read-write AM_INVALID_TR_IE_0 Disabled 0 AM_INVALID_TR_IE_1 Enabled 1 DCDC_ERROR_IE DC-DC error interrupt enable 6 1 read-write DCDC_ERROR_IE_0 Disabled 0 DCDC_ERROR_IE_1 Enabled 1 LPM_INVALID_CLK_IE LPM invalid clock interrupt enable 1 1 read-write LPM_INVALID_CLK_IE_0 Disabled 0 LPM_INVALID_CLK_IE_1 Enabled 1 LPM_INVALID_TR_IE LPM invalid transition interrupt enable 0 1 read-write LPM_INVALID_TR_IE_0 Disabled 0 LPM_INVALID_TR_IE_1 Enabled 1 PCMIFG IFG Interrupt Flag Register 0xC 32 read-only n 0x0 0xFFFFFFFF AM_INVALID_TR_IFG Active mode invalid transition flag 2 1 read-only DCDC_ERROR_IFG DC-DC error flag 6 1 read-only LPM_INVALID_CLK_IFG LPM invalid clock flag 1 1 read-only LPM_INVALID_TR_IFG LPM invalid transition flag 0 1 read-only PMAP PMAP PMAP 0x40005000 0x0 0x40 registers n P1MAP01 P1MAP01 Port mapping register, P1.0 and P1.1 0x8 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P1MAP23 P1MAP23 Port mapping register, P1.2 and P1.3 0xA 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P1MAP45 P1MAP45 Port mapping register, P1.4 and P1.5 0xC 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P1MAP67 P1MAP67 Port mapping register, P1.6 and P1.7 0xE 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P2MAP01 P2MAP01 Port mapping register, P2.0 and P2.1 0x10 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P2MAP23 P2MAP23 Port mapping register, P2.2 and P2.3 0x12 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P2MAP45 P2MAP45 Port mapping register, P2.4 and P2.5 0x14 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P2MAP67 P2MAP67 Port mapping register, P2.6 and P2.7 0x16 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P3MAP01 P3MAP01 Port mapping register, P3.0 and P3.1 0x18 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P3MAP23 P3MAP23 Port mapping register, P3.2 and P3.3 0x1A 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P3MAP45 P3MAP45 Port mapping register, P3.4 and P3.5 0x1C 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P3MAP67 P3MAP67 Port mapping register, P3.6 and P3.7 0x1E 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P4MAP01 P4MAP01 Port mapping register, P4.0 and P4.1 0x20 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P4MAP23 P4MAP23 Port mapping register, P4.2 and P4.3 0x22 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P4MAP45 P4MAP45 Port mapping register, P4.4 and P4.5 0x24 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P4MAP67 P4MAP67 Port mapping register, P4.6 and P4.7 0x26 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P5MAP01 P5MAP01 Port mapping register, P5.0 and P5.1 0x28 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P5MAP23 P5MAP23 Port mapping register, P5.2 and P5.3 0x2A 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P5MAP45 P5MAP45 Port mapping register, P5.4 and P5.5 0x2C 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P5MAP67 P5MAP67 Port mapping register, P5.6 and P5.7 0x2E 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P6MAP01 P6MAP01 Port mapping register, P6.0 and P6.1 0x30 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P6MAP23 P6MAP23 Port mapping register, P6.2 and P6.3 0x32 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P6MAP45 P6MAP45 Port mapping register, P6.4 and P6.5 0x34 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P6MAP67 P6MAP67 Port mapping register, P6.6 and P6.7 0x36 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P7MAP01 P7MAP01 Port mapping register, P7.0 and P7.1 0x38 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P7MAP23 P7MAP23 Port mapping register, P7.2 and P7.3 0x3A 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P7MAP45 P7MAP45 Port mapping register, P7.4 and P7.5 0x3C 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write P7MAP67 P7MAP67 Port mapping register, P7.6 and P7.7 0x3E 16 read-write n 0x0 0x0 PMAPx Selects secondary port function 0 16 read-write PMAPCTL CTL Port Mapping Control Register 0x2 16 read-write n 0x1 0xFFFF PMAPLOCKED Port mapping lock bit 0 1 read-only PMAPLOCKED_enum_read read PMAPLOCKED_0 Access to mapping registers is granted 0 PMAPLOCKED_1 Access to mapping registers is locked 1 PMAPRECFG Port mapping reconfiguration control bit 1 1 read-write PMAPRECFG_0 Configuration allowed only once 0 PMAPRECFG_1 Allow reconfiguration of port mapping 1 PMAPKEYID KEYID Port Mapping Key Register 0x0 16 read-write n 0x96A5 0xFFFF PMAPKEY Port mapping controller write access key 0 16 read-write PSS PSS PSS 0x40010800 0x0 0x40 registers n PSS_IRQ PSS Interrupt 0 PSSCLRIFG CLRIFG Clear Interrupt Flag Register 0x3C 32 read-write n 0x0 0xFFFFFFFF CLRSVSMHIFG SVSMH clear interrupt flag 1 1 write-only CLRSVSMHIFG_enum_write write CLRSVSMHIFG_0 No effect 0 CLRSVSMHIFG_1 Clear pending interrupt flag 1 PSSCTL0 CTL0 Control 0 Register 0x4 32 read-write n 0x2000 0xFFFFFFFF DCDC_FORCE Force DC-DC regulator operation 10 1 read-write DCDC_FORCE_0 DC-DC regulator operation not forced. Automatic fail-safe mechanism switches the core voltage regulator from DC-DC to LDO when the supply voltage falls below the minimum supply voltage necessary for DC-DC operation. 0 DCDC_FORCE_1 DC-DC regulator operation forced. Automatic fail-safe mechanism is disabled and device continues to operate out of DC-DC regulator. 1 SVMHOE SVSM high-side output enable 6 1 read-write SVMHOE_0 SVSMHIFG bit is not output 0 SVMHOE_1 SVSMHIFG bit is output to the device SVMHOUT pin. The device-specific port logic must be configured accordingly 1 SVMHOUTPOLAL SVMHOUT pin polarity active low 7 1 read-write SVMHOUTPOLAL_0 SVMHOUT is active high. An error condition is signaled by a 1 at the SVMHOUT pin 0 SVMHOUTPOLAL_1 SVMHOUT is active low. An error condition is signaled by a 0 at the SVMHOUT pin 1 SVSMHLP SVSM high-side low power normal performance mode 1 1 read-write SVSMHLP_0 Full performance mode. See the device-specific data sheet for response times. 0 SVSMHLP_1 Low power normal performance mode in LPM3, LPM4, and LPMx.5, full performance in all other modes. See the device-specific data sheet for response times. 1 SVSMHOFF SVSM high-side off 0 1 read-write SVSMHOFF_0 The SVSMH is on 0 SVSMHOFF_1 The SVSMH is off 1 SVSMHS Supply supervisor or monitor selection for the high-side 2 1 read-write SVSMHS_0 Configure as SVSH 0 SVSMHS_1 Configure as SVMH 1 SVSMHTH SVSM high-side reset voltage level 3 3 read-write VCORETRAN Controls core voltage level transition time 12 2 read-write VCORETRAN_0 32 s / 100 mV 0 VCORETRAN_1 64 s / 100 mV 1 VCORETRAN_2 128 s / 100 mV (default) 2 VCORETRAN_3 256 s / 100 mV 3 PSSIE IE Interrupt Enable Register 0x34 32 read-write n 0x0 0xFFFFFFFF SVSMHIE High-side SVSM interrupt enable 1 1 read-write SVSMHIE_0 Interrupt disabled 0 SVSMHIE_1 Interrupt enabled 1 PSSIFG IFG Interrupt Flag Register 0x38 32 read-only n 0x0 0xFFFFFFFF SVSMHIFG High-side SVSM interrupt flag 1 1 read-only SVSMHIFG_enum_read read SVSMHIFG_0 No interrupt pending 0 SVSMHIFG_1 Interrupt due to SVSMH 1 PSSKEY KEY Key Register 0x0 32 read-write n 0xA596 0xFFFFFFFF PSSKEY PSS control key 0 16 read-write REF_A REF_A REF_A 0x40003000 0x0 0xC registers n REFCTL0 CTL0 REF Control Register 0 0x0 16 read-write n 0x0 0x0 BGMODE Bandgap mode 11 1 read-only BGMODE_enum_read read BGMODE_0 Static mode 0 BGMODE_1 Sampled mode 1 REFBGACT Reference bandgap active 9 1 read-only REFBGACT_enum_read read REFBGACT_0 Reference bandgap buffer not active 0 REFBGACT_1 Reference bandgap buffer active 1 REFBGOT Bandgap and bandgap buffer one-time trigger 7 1 read-write REFBGOT_0 No trigger 0 REFBGOT_1 Generation of the bandgap voltage is started by writing 1 or by a hardware trigger 1 REFBGRDY Buffered bandgap voltage ready status 13 1 read-only REFBGRDY_enum_read read REFBGRDY_0 Buffered bandgap voltage is not ready to be used 0 REFBGRDY_1 Buffered bandgap voltage is ready to be used 1 REFGENACT Reference generator active 8 1 read-only REFGENACT_enum_read read REFGENACT_0 Reference generator not active 0 REFGENACT_1 Reference generator active 1 REFGENBUSY Reference generator busy 10 1 read-only REFGENBUSY_enum_read read REFGENBUSY_0 Reference generator not busy 0 REFGENBUSY_1 Reference generator busy 1 REFGENOT Reference generator one-time trigger 6 1 read-write REFGENOT_0 No trigger 0 REFGENOT_1 Generation of the reference voltage is started by writing 1 or by a hardware trigger 1 REFGENRDY Variable reference voltage ready status 12 1 read-only REFGENRDY_enum_read read REFGENRDY_0 Reference voltage output is not ready to be used 0 REFGENRDY_1 Reference voltage output is ready to be used 1 REFON Reference enable 0 1 read-write REFON_0 Disables reference if no other reference requests are pending 0 REFON_1 Enables reference in static mode 1 REFOUT Reference output buffer 1 1 read-write REFOUT_0 Reference output not available externally 0 REFOUT_1 Reference output available externally. If ADC14REFBURST = 0, output is available continuously. If ADC14REFBURST = 1, output is available only during an ADC14 conversion. 1 REFTCOFF Temperature sensor disabled 3 1 read-write REFTCOFF_0 Temperature sensor enabled 0 REFTCOFF_1 Temperature sensor disabled to save power 1 REFVSEL Reference voltage level select 4 2 read-write REFVSEL_0 1.2 V available when reference requested or REFON = 1 0 REFVSEL_1 1.45 V available when reference requested or REFON = 1 1 REFVSEL_3 2.5 V available when reference requested or REFON = 1 3 RSTCTL RSTCTL RSTCTL 0xE0042000 0x0 0x128 registers n CSRESET_CLR CSRESET_CLR CS Reset Status Clear Register 0x124 32 read-write n 0x0 0xFFFFFFFF CLR Write 1 clears the DCOR_SHT Flag in RSTCTL_CSRESET_STAT as well as DCOR_SHTIFG flag in CSIFG register of clock system 0 1 write-only CSRESET_STAT CSRESET_STAT CS Reset Status Register 0x120 32 read-only n 0x0 0xFFFFFFFF DCOR_SHT Indicates if POR was caused by DCO short circuit fault in the external resistor mode 0 1 read-only HARDRESET_CLR HARDRESET_CLR Hard Reset Status Clear Register 0x8 32 read-write n 0x0 0xFFFF0000 SRC0 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 0 1 write-only SRC1 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 1 1 write-only SRC10 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 10 1 write-only SRC11 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 11 1 write-only SRC12 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 12 1 write-only SRC13 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 13 1 write-only SRC14 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 14 1 write-only SRC15 Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG 15 1 write-only SRC2 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 2 1 write-only SRC3 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 3 1 write-only SRC4 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 4 1 write-only SRC5 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 5 1 write-only SRC6 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 6 1 write-only SRC7 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 7 1 write-only SRC8 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 8 1 write-only SRC9 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 9 1 write-only HARDRESET_SET HARDRESET_SET Hard Reset Status Set Register 0xC 32 read-write n 0x0 0xFFFFFFFF SRC0 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 0 1 write-only SRC1 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 1 1 write-only SRC10 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 10 1 write-only SRC11 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 11 1 write-only SRC12 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 12 1 write-only SRC13 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 13 1 write-only SRC14 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 14 1 write-only SRC15 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 15 1 write-only SRC2 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 2 1 write-only SRC3 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 3 1 write-only SRC4 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 4 1 write-only SRC5 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 5 1 write-only SRC6 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 6 1 write-only SRC7 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 7 1 write-only SRC8 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 8 1 write-only SRC9 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 9 1 write-only HARDRESET_STAT HARDRESET_STAT Hard Reset Status Register 0x4 32 read-only n 0x0 0xFFFFFFFF SRC0 Indicates that SRC0 was the source of the Hard Reset 0 1 read-only SRC1 Indicates that SRC1 was the source of the Hard Reset 1 1 read-only SRC10 Indicates that SRC10 was the source of the Hard Reset 10 1 read-only SRC11 Indicates that SRC11 was the source of the Hard Reset 11 1 read-only SRC12 Indicates that SRC12 was the source of the Hard Reset 12 1 read-only SRC13 Indicates that SRC13 was the source of the Hard Reset 13 1 read-only SRC14 Indicates that SRC14 was the source of the Hard Reset 14 1 read-only SRC15 Indicates that SRC15 was the source of the Hard Reset 15 1 read-only SRC2 Indicates that SRC2 was the source of the Hard Reset 2 1 read-only SRC3 Indicates that SRC3 was the source of the Hard Reset 3 1 read-only SRC4 Indicates that SRC4 was the source of the Hard Reset 4 1 read-only SRC5 Indicates that SRC5 was the source of the Hard Reset 5 1 read-only SRC6 Indicates that SRC6 was the source of the Hard Reset 6 1 read-only SRC7 Indicates that SRC7 was the source of the Hard Reset 7 1 read-only SRC8 Indicates that SRC8 was the source of the Hard Reset 8 1 read-only SRC9 Indicates that SRC9 was the source of the Hard Reset 9 1 read-only PCMRESET_CLR PCMRESET_CLR PCM Reset Status Clear Register 0x10C 32 read-write n 0x0 0xFFFFFFFF CLR Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT 0 1 write-only PCMRESET_STAT PCMRESET_STAT PCM Reset Status Register 0x108 32 read-only n 0x0 0xFFFFFFFF LPM35 Indicates if POR was caused by PCM due to an exit from LPM3.5 0 1 read-only LPM45 Indicates if POR was caused by PCM due to an exit from LPM4.5 1 1 read-only PINRESET_CLR PINRESET_CLR Pin Reset Status Clear Register 0x114 32 read-write n 0x0 0xFFFFFFFF CLR Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT 0 1 write-only PINRESET_STAT PINRESET_STAT Pin Reset Status Register 0x110 32 read-only n 0x0 0xFFFFFFFF RSTNMI POR was caused by RSTn/NMI pin based reset event 0 1 read-only PSSRESET_CLR PSSRESET_CLR PSS Reset Status Clear Register 0x104 32 read-write n 0x0 0xFFFFFFFF CLR Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT 0 1 write-only PSSRESET_STAT PSSRESET_STAT PSS Reset Status Register 0x100 32 read-only n 0xF 0xFFFFFFFF BGREF Indicates if POR was caused by a BGREF not okay condition in the PSS 2 1 read-only SVSL Indicates if POR was caused by an SVSL trip condition in the PSS 0 1 read-only SVSMH Indicates if POR was caused by an SVSMH trip condition int the PSS 1 1 read-only VCCDET Indicates if POR was caused by a VCCDET trip condition in the PSS 3 1 read-only REBOOTRESET_CLR REBOOTRESET_CLR Reboot Reset Status Clear Register 0x11C 32 read-write n 0x0 0xFFFFFFFF CLR Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT 0 1 write-only REBOOTRESET_STAT REBOOTRESET_STAT Reboot Reset Status Register 0x118 32 read-only n 0x0 0xFFFFFFFF REBOOT Indicates if Reboot reset was caused by the SYSCTL module. 0 1 read-only RESET_REQ RESET_REQ Reset Request Register 0x0 32 read-write n 0x0 0xFFFF00FC HARD_REQ Hard Reset request 1 1 write-only RSTKEY Write key to unlock reset request bits 8 8 write-only SOFT_REQ Soft Reset request 0 1 write-only SOFTRESET_CLR SOFTRESET_CLR Soft Reset Status Clear Register 0x14 32 read-write n 0x0 0xFFFFFFFF SRC0 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 0 1 write-only SRC1 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 1 1 write-only SRC10 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 10 1 write-only SRC11 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 11 1 write-only SRC12 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 12 1 write-only SRC13 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 13 1 write-only SRC14 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 14 1 write-only SRC15 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 15 1 write-only SRC2 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 2 1 write-only SRC3 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 3 1 write-only SRC4 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 4 1 write-only SRC5 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 5 1 write-only SRC6 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 6 1 write-only SRC7 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 7 1 write-only SRC8 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 8 1 write-only SRC9 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 9 1 write-only SOFTRESET_SET SOFTRESET_SET Soft Reset Status Set Register 0x18 32 read-write n 0x0 0xFFFFFFFF SRC0 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 0 1 write-only SRC1 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 1 1 write-only SRC10 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 10 1 write-only SRC11 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 11 1 write-only SRC12 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 12 1 write-only SRC13 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 13 1 write-only SRC14 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 14 1 write-only SRC15 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 15 1 write-only SRC2 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 2 1 write-only SRC3 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 3 1 write-only SRC4 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 4 1 write-only SRC5 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 5 1 write-only SRC6 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 6 1 write-only SRC7 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 7 1 write-only SRC8 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 8 1 write-only SRC9 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 9 1 write-only SOFTRESET_STAT SOFTRESET_STAT Soft Reset Status Register 0x10 32 read-only n 0x0 0xFFFFFFFF SRC0 If 1, indicates that SRC0 was the source of the Soft Reset 0 1 read-only SRC1 If 1, indicates that SRC1 was the source of the Soft Reset 1 1 read-only SRC10 If 1, indicates that SRC10 was the source of the Soft Reset 10 1 read-only SRC11 If 1, indicates that SRC11 was the source of the Soft Reset 11 1 read-only SRC12 If 1, indicates that SRC12 was the source of the Soft Reset 12 1 read-only SRC13 If 1, indicates that SRC13 was the source of the Soft Reset 13 1 read-only SRC14 If 1, indicates that SRC14 was the source of the Soft Reset 14 1 read-only SRC15 If 1, indicates that SRC15 was the source of the Soft Reset 15 1 read-only SRC2 If 1, indicates that SRC2 was the source of the Soft Reset 2 1 read-only SRC3 If 1, indicates that SRC3 was the source of the Soft Reset 3 1 read-only SRC4 If 1, indicates that SRC4 was the source of the Soft Reset 4 1 read-only SRC5 If 1, indicates that SRC5 was the source of the Soft Reset 5 1 read-only SRC6 If 1, indicates that SRC6 was the source of the Soft Reset 6 1 read-only SRC7 If 1, indicates that SRC7 was the source of the Soft Reset 7 1 read-only SRC8 If 1, indicates that SRC8 was the source of the Soft Reset 8 1 read-only SRC9 If 1, indicates that SRC9 was the source of the Soft Reset 9 1 read-only RTC_C RTC_C RTC_C 0x40004400 0x0 0x20 registers n RTC_C_IRQ RTC_C Interrupt 29 RTCADOWDAY ADOWDAY RTCADOWDAY - Hexadecimal Format 0x1A 16 read-write n 0x0 0x6078 DAYAE Alarm enable 15 1 read-write DayofMonth Day of month (1 to 28, 29, 30, 31) 8 5 read-write DayofWeek Day of week (0 to 6) 0 3 read-write DOWAE Alarm enable 7 1 read-write RTCAMINHR AMINHR RTCMINHR - Hexadecimal Format 0x18 16 read-write n 0x0 0x6040 HOURAE Alarm enable 15 1 read-write Hours Hours (0 to 23) 8 5 read-write MINAE Alarm enable 7 1 read-write Minutes Minutes (0 to 59) 0 6 read-write RTCBCD2BIN BCD2BIN BCD-to-Binary Conversion Register 0x1E 16 read-write n 0x0 0xFFFF BCD2BIN bcd to bin conversion 0 16 read-write RTCBIN2BCD BIN2BCD Binary-to-BCD Conversion Register 0x1C 16 read-write n 0x0 0xFFFF BIN2BCD bin to bcd conversion 0 16 read-write RTCCTL0 CTL0 RTCCTL0 Register 0x0 16 read-write n 0x9608 0xFFFF RTCAIE Real-time clock alarm interrupt enable 5 1 read-write RTCAIE_0 Interrupt not enabled 0 RTCAIE_1 Interrupt enabled (LPM3/LPM3.5 wake-up enabled) 1 RTCAIFG Real-time clock alarm interrupt flag 1 1 read-write RTCAIFG_0 No time event occurred 0 RTCAIFG_1 Time event occurred 1 RTCKEY Real-time clock key 8 8 read-write RTCOFIE 32-kHz crystal oscillator fault interrupt enable 7 1 read-write RTCOFIE_0 Interrupt not enabled 0 RTCOFIE_1 Interrupt enabled (LPM3/LPM3.5 wake-up enabled) 1 RTCOFIFG 32-kHz crystal oscillator fault interrupt flag 3 1 read-write RTCOFIFG_0 No interrupt pending 0 RTCOFIFG_1 Interrupt pending. A 32-kHz crystal oscillator fault occurred after last reset. 1 RTCRDYIE Real-time clock ready interrupt enable 4 1 read-write RTCRDYIE_0 Interrupt not enabled 0 RTCRDYIE_1 Interrupt enabled 1 RTCRDYIFG Real-time clock ready interrupt flag 0 1 read-write RTCRDYIFG_0 RTC cannot be read safely 0 RTCRDYIFG_1 RTC can be read safely 1 RTCTEVIE Real-time clock time event interrupt enable 6 1 read-write RTCTEVIE_0 Interrupt not enabled 0 RTCTEVIE_1 Interrupt enabled (LPM3/LPM3.5 wake-up enabled) 1 RTCTEVIFG Real-time clock time event interrupt flag 2 1 read-write RTCTEVIFG_0 No time event occurred 0 RTCTEVIFG_1 Time event occurred 1 RTCCTL13 CTL13 RTCCTL13 Register 0x2 16 read-write n 0x70 0xFFFF RTCBCD Real-time clock BCD select 7 1 read-write RTCBCD_0 Binary (hexadecimal) code selected 0 RTCBCD_1 Binary coded decimal (BCD) code selected 1 RTCCALF Real-time clock calibration frequency 8 2 read-write RTCCALF_0 No frequency output to RTCCLK pin 0 RTCCALF_1 512 Hz 1 RTCCALF_2 256 Hz 2 RTCCALF_3 1 Hz 3 RTCHOLD Real-time clock hold 6 1 read-write RTCHOLD_0 Real-time clock is operational 0 RTCHOLD_1 When set, the calendar is stopped as well as the prescale counters, RT0PS and RT1PS are don't care 1 RTCMODE 5 1 read-only RTCMODE_enum_read read RTCMODE_1 Calendar mode. Always reads a value of 1. 1 RTCRDY Real-time clock ready 4 1 read-only RTCRDY_enum_read read RTCRDY_0 RTC time values in transition 0 RTCRDY_1 RTC time values safe for reading. This bit indicates when the real-time clock time values are safe for reading. 1 RTCSSEL Real-time clock source select 2 2 read-write RTCSSEL_0 BCLK 0 RTCTEV Real-time clock time event 0 2 read-write RTCTEV_0 Minute changed 0 RTCTEV_1 Hour changed 1 RTCTEV_2 Every day at midnight (00:00) 2 RTCTEV_3 Every day at noon (12:00) 3 RTCDATE DATE RTCDATE - Hexadecimal Format 0x14 16 read-write n 0x0 0xF0E0 Day Day of month (1 to 28, 29, 30, 31) 0 5 read-write Month Month (1 to 12) 8 4 read-write RTCIV IV Real-Time Clock Interrupt Vector Register 0xE 16 read-only n 0x0 0xFFFF RTCIV Real-time clock interrupt vector value 0 16 read-only RTCIV_enum_read read RTCIV_0 No interrupt pending 0 RTCIV_10 Interrupt Source: RTC prescaler 0 Interrupt Flag: RT0PSIFG 10 RTCIV_12 Interrupt Source: RTC prescaler 1 Interrupt Flag: RT1PSIFG 12 RTCIV_2 Interrupt Source: RTC oscillator failure Interrupt Flag: RTCOFIFG Interrupt Priority: Highest 2 RTCIV_4 Interrupt Source: RTC ready Interrupt Flag: RTCRDYIFG 4 RTCIV_6 Interrupt Source: RTC interval timer Interrupt Flag: RTCTEVIFG 6 RTCIV_8 Interrupt Source: RTC user alarm Interrupt Flag: RTCAIFG 8 RTCOCAL OCAL RTCOCAL Register 0x4 16 read-write n 0x0 0xFFFF RTCOCAL Real-time clock offset error calibration 0 8 read-write RTCOCALS Real-time clock offset error calibration sign 15 1 read-write RTCOCALS_0 Down calibration. Frequency adjusted down. 0 RTCOCALS_1 Up calibration. Frequency adjusted up. 1 RTCPS PS Real-Time Clock Prescale Timer Counter Register 0xC 16 read-write n 0x0 0x0 RT0PS Prescale timer 0 counter value 0 8 read-write RT1PS Prescale timer 1 counter value 8 8 read-write RTCPS0CTL PS0CTL Real-Time Clock Prescale Timer 0 Control Register 0x8 16 read-write n 0x0 0xFFFF RT0IP Prescale timer 0 interrupt interval 2 3 read-write RT0IP_0 Divide by 2 0 RT0IP_1 Divide by 4 1 RT0IP_2 Divide by 8 2 RT0IP_3 Divide by 16 3 RT0IP_4 Divide by 32 4 RT0IP_5 Divide by 64 5 RT0IP_6 Divide by 128 6 RT0IP_7 Divide by 256 7 RT0PSIE Prescale timer 0 interrupt enable 1 1 read-write RT0PSIE_0 Interrupt not enabled 0 RT0PSIE_1 Interrupt enabled (LPM3/LPM3.5 wake-up enabled) 1 RT0PSIFG Prescale timer 0 interrupt flag 0 1 read-write RT0PSIFG_0 No time event occurred 0 RT0PSIFG_1 Time event occurred 1 RTCPS1CTL PS1CTL Real-Time Clock Prescale Timer 1 Control Register 0xA 16 read-write n 0x0 0xFFFF RT1IP Prescale timer 1 interrupt interval 2 3 read-write RT1IP_0 Divide by 2 0 RT1IP_1 Divide by 4 1 RT1IP_2 Divide by 8 2 RT1IP_3 Divide by 16 3 RT1IP_4 Divide by 32 4 RT1IP_5 Divide by 64 5 RT1IP_6 Divide by 128 6 RT1IP_7 Divide by 256 7 RT1PSIE Prescale timer 1 interrupt enable 1 1 read-write RT1PSIE_0 Interrupt not enabled 0 RT1PSIE_1 Interrupt enabled (LPM3/LPM3.5 wake-up enabled) 1 RT1PSIFG Prescale timer 1 interrupt flag 0 1 read-write RT1PSIFG_0 No time event occurred 0 RT1PSIFG_1 Time event occurred 1 RTCTCMP TCMP RTCTCMP Register 0x6 16 read-write n 0x4000 0xFFFF RTCTCMP Real-time clock temperature compensation 0 8 read-write RTCTCMPS Real-time clock temperature compensation sign 15 1 read-write RTCTCMPS_0 Down calibration. Frequency adjusted down 0 RTCTCMPS_1 Up calibration. Frequency adjusted up 1 RTCTCOK Real-time clock temperature compensation write OK 13 1 read-only RTCTCOK_enum_read read RTCTCOK_0 Write to RTCTCMPx is unsuccessful 0 RTCTCOK_1 Write to RTCTCMPx is successful 1 RTCTCRDY Real-time clock temperature compensation ready 14 1 read-only RTCTIM0 TIM0 RTCTIM0 Register Hexadecimal Format 0x10 16 read-write n 0x0 0xC0C0 Minutes Minutes (0 to 59) 8 6 read-write Seconds Seconds (0 to 59) 0 6 read-write RTCTIM1 TIM1 Real-Time Clock Hour, Day of Week 0x12 16 read-write n 0x0 0xF8E0 DayofWeek Day of week (0 to 6) 8 3 read-write Hours Hours (0 to 23) 0 5 read-write RTCYEAR YEAR RTCYEAR Register Hexadecimal Format 0x16 16 read-write n 0x0 0xF000 YearHighByte Year high byte. Valid values for Year are 0 to 4095. 8 4 read-write YearLowByte Year low byte. Valid values for Year are 0 to 4095. 0 8 read-write SYSCTL_A SYSCTL_A SYSCTL_A 0xE0043000 0x0 0x102C registers n SYS_BOOTOVER_ACK BOOTOVER_ACK Boot Override Acknowledge Register 0x100C 32 read-write n 0x0 0xFFFFFFFF REGVAL Value set by CPU, read/clear by the debugger 0 32 read-write SYS_BOOTOVER_REQ0 BOOTOVER_REQ0 Boot Override Request Register 0x1004 32 read-write n 0x0 0xFFFFFFFF REGVAL Value set by debugger, read and clear by the CPU 0 32 read-write SYS_BOOTOVER_REQ1 BOOTOVER_REQ1 Boot Override Request Register 0x1008 32 read-write n 0x0 0xFFFFFFFF REGVAL Value set by debugger, read and clear by the CPU 0 32 read-write SYS_BOOTOVER_REQ[0] BOOTOVER_REQ[%s] Boot Override Request Register 0x2008 32 read-write n 0x0 0xFFFFFFFF REGVAL Value set by debugger, read and clear by the CPU 0 32 read-write SYS_BOOTOVER_REQ[1] BOOTOVER_REQ[%s] Boot Override Request Register 0x3010 32 read-write n 0x0 0xFFFFFFFF REGVAL Value set by debugger, read and clear by the CPU 0 32 read-write SYS_DIO_GLTFLT_CTL DIO_GLTFLT_CTL Digital I/O Glitch Filter Control Register 0x30 32 read-write n 0x1 0xFFFFFFFF GLTCH_EN Glitch filter enable 0 1 read-write GLTCH_EN_0 Disables glitch filter on the digital I/Os 0 GLTCH_EN_1 Enables glitch filter on the digital I/Os 1 SYS_INFOFLASH_SIZE INFOFLASH_SIZE Flash Information Memory Size Register 0x24 32 read-only n 0x0 0x0 SIZE Flash information memory size 0 32 read-only SYS_MAINFLASH_SIZE MAINFLASH_SIZE Flash Main Memory Size Register 0x20 32 read-only n 0x0 0x0 SIZE Flash main memory size 0 32 read-only SYS_MASTER_UNLOCK MASTER_UNLOCK Master Unlock Register 0x1000 32 read-write n 0x0 0xFFFFFFFF UNLKEY Unlock Key 0 16 read-write SYS_NMI_CTLSTAT NMI_CTLSTAT NMI Control and Status Register 0x4 32 read-write n 0x7 0xFFFFFFFF CS_FLG CS interrupt was the source of NMI 16 1 read-only CS_FLG_enum_read read CS_FLG_0 indicates CS interrupt was not the source of NMI 0 CS_FLG_1 indicates CS interrupt was the source of NMI 1 CS_SRC CS interrupt as a source of NMI 0 1 read-write CS_SRC_0 Disables CS interrupt as a source of NMI 0 CS_SRC_1 Enables CS interrupt as a source of NMI 1 PCM_FLG PCM interrupt was the source of NMI 18 1 read-only PCM_FLG_enum_read read PCM_FLG_0 indicates the PCM interrupt was not the source of NMI 0 PCM_FLG_1 indicates the PCM interrupt was the source of NMI 1 PCM_SRC PCM interrupt as a source of NMI 2 1 read-write PCM_SRC_0 Disbles the PCM interrupt as a source of NMI 0 PCM_SRC_1 Enables the PCM interrupt as a source of NMI 1 PIN_FLG RSTn/NMI pin was the source of NMI 19 1 read-write PIN_FLG_0 Indicates the RSTn_NMI pin was not the source of NMI 0 PIN_FLG_1 Indicates the RSTn_NMI pin was the source of NMI 1 PIN_SRC RSTn/NMI pin configuration Note: When the device enters LPM3/LPM4 modes of operation, the functionality selected by this bit is retained. If selected as an NMI, activity on this pin in LPM3/LPM4 wakes the device and processes the interrupt, without causing a POR. If selected as a Reset, activity on this pin in LPM3/LPM4 causes a device-level POR When the device enters LPM3.5/LPM4.5 modes of operation, this bit is always cleared to 0. In other words, the RSTn/NMI pin always assumes a reset functionality in LPM3.5/LPM4.5 modes. 3 1 read-write PIN_SRC_0 Configures the RSTn_NMI pin as a source of POR Class Reset 0 PIN_SRC_1 Configures the RSTn_NMI pin as a source of NMI 1 PSS_FLG PSS interrupt was the source of NMI 17 1 read-only PSS_FLG_enum_read read PSS_FLG_0 indicates the PSS interrupt was not the source of NMI 0 PSS_FLG_1 indicates the PSS interrupt was the source of NMI 1 PSS_SRC PSS interrupt as a source of NMI 1 1 read-write PSS_SRC_0 Disables the PSS interrupt as a source of NMI 0 PSS_SRC_1 Enables the PSS interrupt as a source of NMI 1 SYS_PERIHALT_CTL PERIHALT_CTL Peripheral Halt Control Register 0xC 32 read-write n 0x4000 0xFFFFFFFF HALT_ADC Freezes IP operation when CPU is halted 13 1 read-write HALT_ADC_0 IP operation unaffected when CPU is halted 0 HALT_ADC_1 freezes IP operation when CPU is halted 1 HALT_DMA Freezes IP operation when CPU is halted 15 1 read-write HALT_DMA_0 IP operation unaffected when CPU is halted 0 HALT_DMA_1 freezes IP operation when CPU is halted 1 HALT_eUA0 Freezes IP operation when CPU is halted 5 1 read-write HALT_eUA0_0 IP operation unaffected when CPU is halted 0 HALT_eUA0_1 freezes IP operation when CPU is halted 1 HALT_eUA1 Freezes IP operation when CPU is halted 6 1 read-write HALT_eUA1_0 IP operation unaffected when CPU is halted 0 HALT_eUA1_1 freezes IP operation when CPU is halted 1 HALT_eUA2 Freezes IP operation when CPU is halted 7 1 read-write HALT_eUA2_0 IP operation unaffected when CPU is halted 0 HALT_eUA2_1 freezes IP operation when CPU is halted 1 HALT_eUA3 Freezes IP operation when CPU is halted 8 1 read-write HALT_eUA3_0 IP operation unaffected when CPU is halted 0 HALT_eUA3_1 freezes IP operation when CPU is halted 1 HALT_eUB0 Freezes IP operation when CPU is halted 9 1 read-write HALT_eUB0_0 IP operation unaffected when CPU is halted 0 HALT_eUB0_1 freezes IP operation when CPU is halted 1 HALT_eUB1 Freezes IP operation when CPU is halted 10 1 read-write HALT_eUB1_0 IP operation unaffected when CPU is halted 0 HALT_eUB1_1 freezes IP operation when CPU is halted 1 HALT_eUB2 Freezes IP operation when CPU is halted 11 1 read-write HALT_eUB2_0 IP operation unaffected when CPU is halted 0 HALT_eUB2_1 freezes IP operation when CPU is halted 1 HALT_eUB3 Freezes IP operation when CPU is halted 12 1 read-write HALT_eUB3_0 IP operation unaffected when CPU is halted 0 HALT_eUB3_1 freezes IP operation when CPU is halted 1 HALT_LCD Freezes IP operation when CPU is halted 16 1 read-write HALT_LCD_0 IP operation unaffected when CPU is halted 0 HALT_LCD_1 freezes IP operation when CPU is halted 1 HALT_T16_0 Freezes IP operation when CPU is halted 0 1 read-write HALT_T16_0_0 IP operation unaffected when CPU is halted 0 HALT_T16_0_1 freezes IP operation when CPU is halted 1 HALT_T16_1 Freezes IP operation when CPU is halted 1 1 read-write HALT_T16_1_0 IP operation unaffected when CPU is halted 0 HALT_T16_1_1 freezes IP operation when CPU is halted 1 HALT_T16_2 Freezes IP operation when CPU is halted 2 1 read-write HALT_T16_2_0 IP operation unaffected when CPU is halted 0 HALT_T16_2_1 freezes IP operation when CPU is halted 1 HALT_T16_3 Freezes IP operation when CPU is halted 3 1 read-write HALT_T16_3_0 IP operation unaffected when CPU is halted 0 HALT_T16_3_1 freezes IP operation when CPU is halted 1 HALT_T32_0 Freezes IP operation when CPU is halted 4 1 read-write HALT_T32_0_0 IP operation unaffected when CPU is halted 0 HALT_T32_0_1 freezes IP operation when CPU is halted 1 HALT_WDT Freezes IP operation when CPU is halted 14 1 read-write HALT_WDT_0 IP operation unaffected when CPU is halted 0 HALT_WDT_1 freezes IP operation when CPU is halted 1 SYS_REBOOT_CTL REBOOT_CTL Reboot Control Register 0x0 32 read-write n 0xFE 0xFFFFFFFF REBOOT Write 1 initiates a Reboot of the device 0 1 write-only WKEY Key to enable writes to bit 0 8 8 write-only SYS_RESET_REQ RESET_REQ Reset Request Register 0x1010 32 read-write n 0x0 0x0 POR Generate POR 0 1 write-only REBOOT Generate Reboot_Reset 1 1 write-only WKEY Write key 8 8 write-only SYS_RESET_STATOVER RESET_STATOVER Reset Status and Override Register 0x1014 32 read-write n 0x0 0x700 HARD Indicates if HARD Reset is active 1 1 read-only HARD_OVER HARD_Reset overwrite request 9 1 read-write RBT_OVER Reboot Reset overwrite request 10 1 read-write REBOOT Indicates if Reboot Reset is active 2 1 read-only SOFT Indicates if SOFT Reset is active 0 1 read-only SOFT_OVER SOFT_Reset overwrite request 8 1 read-write SYS_SECDATA_UNLOCK SECDATA_UNLOCK IP Protected Secure Zone Data Access Unlock Register 0x40 32 read-write n 0x0 0xFFFFFFFF UNLKEY Unlock key 0 16 read-write SYS_SRAM_BANKEN_CTL0 SRAM_BANKEN_CTL0 SRAM Bank Enable Control Register 0 0x50 32 read-write n 0xFFFFFFFF 0xFFFFFFFF BNK0_EN When 1, enables Bank0 of the SRAM 0 1 read-only BNK10_EN When 1, enables Bank10 of the SRAM 10 1 read-write BNK10_EN_0 Disables Bank10 of the SRAM 0 BNK10_EN_1 Enables Bank10 of the SRAM 1 BNK11_EN When 1, enables Bank11 of the SRAM 11 1 read-write BNK11_EN_0 Disables Bank11 of the SRAM 0 BNK11_EN_1 Enables Bank11 of the SRAM 1 BNK12_EN When 1, enables Bank12 of the SRAM 12 1 read-write BNK12_EN_0 Disables Bank12 of the SRAM 0 BNK12_EN_1 Enables Bank12 of the SRAM 1 BNK13_EN When 1, enables Bank13 of the SRAM 13 1 read-write BNK13_EN_0 Disables Bank13 of the SRAM 0 BNK13_EN_1 Enables Bank13 of the SRAM 1 BNK14_EN When 1, enables Bank14 of the SRAM 14 1 read-write BNK14_EN_0 Disables Bank14 of the SRAM 0 BNK14_EN_1 Enables Bank14 of the SRAM 1 BNK15_EN When 1, enables Bank15 of the SRAM 15 1 read-write BNK15_EN_0 Disables Bank15 of the SRAM 0 BNK15_EN_1 Enables Bank15 of the SRAM 1 BNK16_EN When 1, enables Bank16 of the SRAM 16 1 read-write BNK16_EN_0 Disables Bank16 of the SRAM 0 BNK16_EN_1 Enables Bank16 of the SRAM 1 BNK17_EN When 1, enables Bank17 of the SRAM 17 1 read-write BNK17_EN_0 Disables Bank17 of the SRAM 0 BNK17_EN_1 Enables Bank17 of the SRAM 1 BNK18_EN When 1, enables Bank18 of the SRAM 18 1 read-write BNK18_EN_0 Disables Bank18 of the SRAM 0 BNK18_EN_1 Enables Bank18 of the SRAM 1 BNK19_EN When 1, enables Bank19 of the SRAM 19 1 read-write BNK19_EN_0 Disables Bank19 of the SRAM 0 BNK19_EN_1 Enables Bank19 of the SRAM 1 BNK1_EN When 1, enables Bank1 of the SRAM 1 1 read-write BNK1_EN_0 Disables Bank1 of the SRAM 0 BNK1_EN_1 Enables Bank1 of the SRAM 1 BNK20_EN When 1, enables Bank20 of the SRAM 20 1 read-write BNK20_EN_0 Disables Bank20 of the SRAM 0 BNK20_EN_1 Enables Bank20 of the SRAM 1 BNK21_EN When 1, enables Bank21 of the SRAM 21 1 read-write BNK21_EN_0 Disables Bank21 of the SRAM 0 BNK21_EN_1 Enables Bank21 of the SRAM 1 BNK22_EN When 1, enables Bank22 of the SRAM 22 1 read-write BNK22_EN_0 Disables Bank22 of the SRAM 0 BNK22_EN_1 Enables Bank22 of the SRAM 1 BNK23_EN When 1, enables Bank23 of the SRAM 23 1 read-write BNK23_EN_0 Disables Bank23 of the SRAM 0 BNK23_EN_1 Enables Bank23 of the SRAM 1 BNK24_EN When 1, enables Bank24 of the SRAM 24 1 read-write BNK24_EN_0 Disables Bank24 of the SRAM 0 BNK24_EN_1 Enables Bank24 of the SRAM 1 BNK25_EN When 1, enables Bank25 of the SRAM 25 1 read-write BNK25_EN_0 Disables Bank25 of the SRAM 0 BNK25_EN_1 Enables Bank25 of the SRAM 1 BNK26_EN When 1, enables Bank26 of the SRAM 26 1 read-write BNK26_EN_0 Disables Bank26 of the SRAM 0 BNK26_EN_1 Enables Bank26 of the SRAM 1 BNK27_EN When 1, enables Bank27 of the SRAM 27 1 read-write BNK27_EN_0 Disables Bank27 of the SRAM 0 BNK27_EN_1 Enables Bank27 of the SRAM 1 BNK28_EN When 1, enables Bank28 of the SRAM 28 1 read-write BNK28_EN_0 Disables Bank28 of the SRAM 0 BNK28_EN_1 Enables Bank28 of the SRAM 1 BNK29_EN When 1, enables Bank29 of the SRAM 29 1 read-write BNK29_EN_0 Disables Bank29 of the SRAM 0 BNK29_EN_1 Enables Bank29 of the SRAM 1 BNK2_EN When 1, enables Bank2 of the SRAM 2 1 read-write BNK2_EN_0 Disables Bank2 of the SRAM 0 BNK2_EN_1 Enables Bank2 of the SRAM 1 BNK30_EN When 1, enables Bank30 of the SRAM 30 1 read-write BNK30_EN_0 Disables Bank30 of the SRAM 0 BNK30_EN_1 Enables Bank30 of the SRAM 1 BNK31_EN When 1, enables Bank31 of the SRAM 31 1 read-write BNK31_EN_0 Disables Bank31 of the SRAM 0 BNK31_EN_1 Enables Bank31 of the SRAM 1 BNK3_EN When 1, enables Bank3 of the SRAM 3 1 read-write BNK3_EN_0 Disables Bank3 of the SRAM 0 BNK3_EN_1 Enables Bank3 of the SRAM 1 BNK4_EN When 1, enables Bank4 of the SRAM 4 1 read-write BNK4_EN_0 Disables Bank4 of the SRAM 0 BNK4_EN_1 Enables Bank4 of the SRAM 1 BNK5_EN When 1, enables Bank5 of the SRAM 5 1 read-write BNK5_EN_0 Disables Bank5 of the SRAM 0 BNK5_EN_1 Enables Bank5 of the SRAM 1 BNK6_EN When 1, enables Bank6 of the SRAM 6 1 read-write BNK6_EN_0 Disables Bank6 of the SRAM 0 BNK6_EN_1 Enables Bank6 of the SRAM 1 BNK7_EN When 1, enables Bank7 of the SRAM 7 1 read-write BNK7_EN_0 Disables Bank7 of the SRAM 0 BNK7_EN_1 Enables Bank7 of the SRAM 1 BNK8_EN When 1, enables Bank8 of the SRAM 8 1 read-write BNK8_EN_0 Disables Bank8 of the SRAM 0 BNK8_EN_1 Enables Bank8 of the SRAM 1 BNK9_EN When 1, enables Bank9 of the SRAM 9 1 read-write BNK9_EN_0 Disables Bank9 of the SRAM 0 BNK9_EN_1 Enables Bank9 of the SRAM 1 SYS_SRAM_BANKEN_CTL1 SRAM_BANKEN_CTL1 SRAM Bank Enable Control Register 1 0x54 32 read-write n 0xFFFFFFFF 0xFFFFFFFF BNK32_EN When 1, enables Bank32 of the SRAM 0 1 read-write BNK32_EN_0 Disables Bank32 of the SRAM 0 BNK32_EN_1 Enables Bank32 of the SRAM 1 BNK33_EN When 1, enables Bank33 of the SRAM 1 1 read-write BNK33_EN_0 Disables Bank33 of the SRAM 0 BNK33_EN_1 Enables Bank33 of the SRAM 1 BNK34_EN When 1, enables Bank34 of the SRAM 2 1 read-write BNK34_EN_0 Disables Bank34 of the SRAM 0 BNK34_EN_1 Enables Bank34 of the SRAM 1 BNK35_EN When 1, enables Bank35 of the SRAM 3 1 read-write BNK35_EN_0 Disables Bank35 of the SRAM 0 BNK35_EN_1 Enables Bank35 of the SRAM 1 BNK36_EN When 1, enables Bank36 of the SRAM 4 1 read-write BNK36_EN_0 Disables Bank36 of the SRAM 0 BNK36_EN_1 Enables Bank36 of the SRAM 1 BNK37_EN When 1, enables Bank37 of the SRAM 5 1 read-write BNK37_EN_0 Disables Bank37 of the SRAM 0 BNK37_EN_1 Enables Bank37 of the SRAM 1 BNK38_EN When 1, enables Bank38 of the SRAM 6 1 read-write BNK38_EN_0 Disables Bank38 of the SRAM 0 BNK38_EN_1 Enables Bank38 of the SRAM 1 BNK39_EN When 1, enables Bank39 of the SRAM 7 1 read-write BNK39_EN_0 Disables Bank39 of the SRAM 0 BNK39_EN_1 Enables Bank39 of the SRAM 1 BNK40_EN When 1, enables Bank40 of the SRAM 8 1 read-write BNK40_EN_0 Disables Bank40 of the SRAM 0 BNK40_EN_1 Enables Bank40 of the SRAM 1 BNK41_EN When 1, enables Bank41 of the SRAM 9 1 read-write BNK41_EN_0 Disables Bank41 of the SRAM 0 BNK41_EN_1 Enables Bank41 of the SRAM 1 BNK42_EN When 1, enables Bank42 of the SRAM 10 1 read-write BNK42_EN_0 Disables Bank42 of the SRAM 0 BNK42_EN_1 Enables Bank42 of the SRAM 1 BNK43_EN When 1, enables Bank43 of the SRAM 11 1 read-write BNK43_EN_0 Disables Bank43 of the SRAM 0 BNK43_EN_1 Enables Bank43 of the SRAM 1 BNK44_EN When 1, enables Bank44 of the SRAM 12 1 read-write BNK44_EN_0 Disables Bank44 of the SRAM 0 BNK44_EN_1 Enables Bank44 of the SRAM 1 BNK45_EN When 1, enables Bank45 of the SRAM 13 1 read-write BNK45_EN_0 Disables Bank45 of the SRAM 0 BNK45_EN_1 Enables Bank45 of the SRAM 1 BNK46_EN When 1, enables Bank46 of the SRAM 14 1 read-write BNK46_EN_0 Disables Bank46 of the SRAM 0 BNK46_EN_1 Enables Bank46 of the SRAM 1 BNK47_EN When 1, enables Bank47 of the SRAM 15 1 read-write BNK47_EN_0 Disables Bank47 of the SRAM 0 BNK47_EN_1 Enables Bank47 of the SRAM 1 BNK48_EN When 1, enables Bank48 of the SRAM 16 1 read-write BNK48_EN_0 Disables Bank48 of the SRAM 0 BNK48_EN_1 Enables Bank48 of the SRAM 1 BNK49_EN When 1, enables Bank49 of the SRAM 17 1 read-write BNK49_EN_0 Disables Bank49 of the SRAM 0 BNK49_EN_1 Enables Bank49 of the SRAM 1 BNK50_EN When 1, enables Bank50 of the SRAM 18 1 read-write BNK50_EN_0 Disables Bank50 of the SRAM 0 BNK50_EN_1 Enables Bank50 of the SRAM 1 BNK51_EN When 1, enables Bank51 of the SRAM 19 1 read-write BNK51_EN_0 Disables Bank51 of the SRAM 0 BNK51_EN_1 Enables Bank51 of the SRAM 1 BNK52_EN When 1, enables Bank52 of the SRAM 20 1 read-write BNK52_EN_0 Disables Bank52 of the SRAM 0 BNK52_EN_1 Enables Bank52 of the SRAM 1 BNK53_EN When 1, enables Bank53 of the SRAM 21 1 read-write BNK53_EN_0 Disables Bank53 of the SRAM 0 BNK53_EN_1 Enables Bank53 of the SRAM 1 BNK54_EN When 1, enables Bank54 of the SRAM 22 1 read-write BNK54_EN_0 Disables Bank54 of the SRAM 0 BNK54_EN_1 Enables Bank54 of the SRAM 1 BNK55_EN When 1, enables Bank55 of the SRAM 23 1 read-write BNK55_EN_0 Disables Bank55 of the SRAM 0 BNK55_EN_1 Enables Bank55 of the SRAM 1 BNK56_EN When 1, enables Bank56 of the SRAM 24 1 read-write BNK56_EN_0 Disables Bank56 of the SRAM 0 BNK56_EN_1 Enables Bank56 of the SRAM 1 BNK57_EN When 1, enables Bank57 of the SRAM 25 1 read-write BNK57_EN_0 Disables Bank57 of the SRAM 0 BNK57_EN_1 Enables Bank57 of the SRAM 1 BNK58_EN When 1, enables Bank58 of the SRAM 26 1 read-write BNK58_EN_0 Disables Bank58 of the SRAM 0 BNK58_EN_1 Enables Bank58 of the SRAM 1 BNK59_EN When 1, enables Bank59 of the SRAM 27 1 read-write BNK59_EN_0 Disables Bank59 of the SRAM 0 BNK59_EN_1 Enables Bank59 of the SRAM 1 BNK60_EN When 1, enables Bank60 of the SRAM 28 1 read-write BNK60_EN_0 Disables Bank60 of the SRAM 0 BNK60_EN_1 Enables Bank60 of the SRAM 1 BNK61_EN When 1, enables Bank61 of the SRAM 29 1 read-write BNK61_EN_0 Disables Bank61 of the SRAM 0 BNK61_EN_1 Enables Bank61 of the SRAM 1 BNK62_EN When 1, enables Bank62 of the SRAM 30 1 read-write BNK62_EN_0 Disables Bank62 of the SRAM 0 BNK62_EN_1 Enables Bank62 of the SRAM 1 BNK63_EN When 1, enables Bank63 of the SRAM 31 1 read-write BNK63_EN_0 Disables Bank63 of the SRAM 0 BNK63_EN_1 Enables Bank63 of the SRAM 1 SYS_SRAM_BANKEN_CTL2 SRAM_BANKEN_CTL2 SRAM Bank Enable Control Register 2 0x58 32 read-write n 0xFFFFFFFF 0xFFFFFFFF BNK64_EN When 1, enables Bank64 of the SRAM 0 1 read-write BNK64_EN_0 Disables Bank64 of the SRAM 0 BNK64_EN_1 Enables Bank64 of the SRAM 1 BNK65_EN When 1, enables Bank65 of the SRAM 1 1 read-write BNK65_EN_0 Disables Bank65 of the SRAM 0 BNK65_EN_1 Enables Bank65 of the SRAM 1 BNK66_EN When 1, enables Bank66 of the SRAM 2 1 read-write BNK66_EN_0 Disables Bank66 of the SRAM 0 BNK66_EN_1 Enables Bank66 of the SRAM 1 BNK67_EN When 1, enables Bank67 of the SRAM 3 1 read-write BNK67_EN_0 Disables Bank67 of the SRAM 0 BNK67_EN_1 Enables Bank67 of the SRAM 1 BNK68_EN When 1, enables Bank68 of the SRAM 4 1 read-write BNK68_EN_0 Disables Bank68 of the SRAM 0 BNK68_EN_1 Enables Bank68 of the SRAM 1 BNK69_EN When 1, enables Bank69 of the SRAM 5 1 read-write BNK69_EN_0 Disables Bank69 of the SRAM 0 BNK69_EN_1 Enables Bank69 of the SRAM 1 BNK70_EN When 1, enables Bank70 of the SRAM 6 1 read-write BNK70_EN_0 Disables Bank70 of the SRAM 0 BNK70_EN_1 Enables Bank70 of the SRAM 1 BNK71_EN When 1, enables Bank71 of the SRAM 7 1 read-write BNK71_EN_0 Disables Bank71 of the SRAM 0 BNK71_EN_1 Enables Bank71 of the SRAM 1 BNK72_EN When 1, enables Bank72 of the SRAM 8 1 read-write BNK72_EN_0 Disables Bank72 of the SRAM 0 BNK72_EN_1 Enables Bank72 of the SRAM 1 BNK73_EN When 1, enables Bank73 of the SRAM 9 1 read-write BNK73_EN_0 Disables Bank73 of the SRAM 0 BNK73_EN_1 Enables Bank73 of the SRAM 1 BNK74_EN When 1, enables Bank74 of the SRAM 10 1 read-write BNK74_EN_0 Disables Bank74 of the SRAM 0 BNK74_EN_1 Enables Bank74 of the SRAM 1 BNK75_EN When 1, enables Bank75 of the SRAM 11 1 read-write BNK75_EN_0 Disables Bank75 of the SRAM 0 BNK75_EN_1 Enables Bank75 of the SRAM 1 BNK76_EN When 1, enables Bank76 of the SRAM 12 1 read-write BNK76_EN_0 Disables Bank76 of the SRAM 0 BNK76_EN_1 Enables Bank76 of the SRAM 1 BNK77_EN When 1, enables Bank77 of the SRAM 13 1 read-write BNK77_EN_0 Disables Bank77 of the SRAM 0 BNK77_EN_1 Enables Bank77 of the SRAM 1 BNK78_EN When 1, enables Bank78 of the SRAM 14 1 read-write BNK78_EN_0 Disables Bank78 of the SRAM 0 BNK78_EN_1 Enables Bank78 of the SRAM 1 BNK79_EN When 1, enables Bank79 of the SRAM 15 1 read-write BNK79_EN_0 Disables Bank79 of the SRAM 0 BNK79_EN_1 Enables Bank79 of the SRAM 1 BNK80_EN When 1, enables Bank80 of the SRAM 16 1 read-write BNK80_EN_0 Disables Bank80 of the SRAM 0 BNK80_EN_1 Enables Bank80 of the SRAM 1 BNK81_EN When 1, enables Bank81 of the SRAM 17 1 read-write BNK81_EN_0 Disables Bank81 of the SRAM 0 BNK81_EN_1 Enables Bank81 of the SRAM 1 BNK82_EN When 1, enables Bank82 of the SRAM 18 1 read-write BNK82_EN_0 Disables Bank82 of the SRAM 0 BNK82_EN_1 Enables Bank82 of the SRAM 1 BNK83_EN When 1, enables Bank83 of the SRAM 19 1 read-write BNK83_EN_0 Disables Bank83 of the SRAM 0 BNK83_EN_1 Enables Bank83 of the SRAM 1 BNK84_EN When 1, enables Bank84 of the SRAM 20 1 read-write BNK84_EN_0 Disables Bank84 of the SRAM 0 BNK84_EN_1 Enables Bank84 of the SRAM 1 BNK85_EN When 1, enables Bank85 of the SRAM 21 1 read-write BNK85_EN_0 Disables Bank85 of the SRAM 0 BNK85_EN_1 Enables Bank85 of the SRAM 1 BNK86_EN When 1, enables Bank86 of the SRAM 22 1 read-write BNK86_EN_0 Disables Bank86 of the SRAM 0 BNK86_EN_1 Enables Bank86 of the SRAM 1 BNK87_EN When 1, enables Bank87 of the SRAM 23 1 read-write BNK87_EN_0 Disables Bank87 of the SRAM 0 BNK87_EN_1 Enables Bank87 of the SRAM 1 BNK88_EN When 1, enables Bank88 of the SRAM 24 1 read-write BNK88_EN_0 Disables Bank88 of the SRAM 0 BNK88_EN_1 Enables Bank88 of the SRAM 1 BNK89_EN When 1, enables Bank89 of the SRAM 25 1 read-write BNK89_EN_0 Disables Bank89 of the SRAM 0 BNK89_EN_1 Enables Bank89 of the SRAM 1 BNK90_EN When 1, enables Bank90 of the SRAM 26 1 read-write BNK90_EN_0 Disables Bank90 of the SRAM 0 BNK90_EN_1 Enables Bank90 of the SRAM 1 BNK91_EN When 1, enables Bank91 of the SRAM 27 1 read-write BNK91_EN_0 Disables Bank91 of the SRAM 0 BNK91_EN_1 Enables Bank91 of the SRAM 1 BNK92_EN When 1, enables Bank92 of the SRAM 28 1 read-write BNK92_EN_0 Disables Bank92 of the SRAM 0 BNK92_EN_1 Enables Bank92 of the SRAM 1 BNK93_EN When 1, enables Bank93 of the SRAM 29 1 read-write BNK93_EN_0 Disables Bank93 of the SRAM 0 BNK93_EN_1 Enables Bank93 of the SRAM 1 BNK94_EN When 1, enables Bank94 of the SRAM 30 1 read-write BNK94_EN_0 Disables Bank94 of the SRAM 0 BNK94_EN_1 Enables Bank94 of the SRAM 1 BNK95_EN When 1, enables Bank95 of the SRAM 31 1 read-write BNK95_EN_0 Disables Bank95 of the SRAM 0 BNK95_EN_1 Enables Bank95 of the SRAM 1 SYS_SRAM_BANKEN_CTL3 SRAM_BANKEN_CTL3 SRAM Bank Enable Control Register 3 0x5C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF BNK100_EN When 1, enables Bank100 of the SRAM 4 1 read-write BNK100_EN_0 Disables Bank100 of the SRAM 0 BNK100_EN_1 Enables Bank100 of the SRAM 1 BNK101_EN When 1, enables Bank101 of the SRAM 5 1 read-write BNK101_EN_0 Disables Bank101 of the SRAM 0 BNK101_EN_1 Enables Bank101 of the SRAM 1 BNK102_EN When 1, enables Bank102 of the SRAM 6 1 read-write BNK102_EN_0 Disables Bank102 of the SRAM 0 BNK102_EN_1 Enables Bank102 of the SRAM 1 BNK103_EN When 1, enables Bank103 of the SRAM 7 1 read-write BNK103_EN_0 Disables Bank103 of the SRAM 0 BNK103_EN_1 Enables Bank103 of the SRAM 1 BNK104_EN When 1, enables Bank104 of the SRAM 8 1 read-write BNK104_EN_0 Disables Bank104 of the SRAM 0 BNK104_EN_1 Enables Bank104 of the SRAM 1 BNK105_EN When 1, enables Bank105 of the SRAM 9 1 read-write BNK105_EN_0 Disables Bank105 of the SRAM 0 BNK105_EN_1 Enables Bank105 of the SRAM 1 BNK106_EN When 1, enables Bank106 of the SRAM 10 1 read-write BNK106_EN_0 Disables Bank106 of the SRAM 0 BNK106_EN_1 Enables Bank106 of the SRAM 1 BNK107_EN When 1, enables Bank107 of the SRAM 11 1 read-write BNK107_EN_0 Disables Bank107 of the SRAM 0 BNK107_EN_1 Enables Bank107 of the SRAM 1 BNK108_EN When 1, enables Bank108 of the SRAM 12 1 read-write BNK108_EN_0 Disables Bank108 of the SRAM 0 BNK108_EN_1 Enables Bank108 of the SRAM 1 BNK109_EN When 1, enables Bank109 of the SRAM 13 1 read-write BNK109_EN_0 Disables Bank109 of the SRAM 0 BNK109_EN_1 Enables Bank109 of the SRAM 1 BNK110_EN When 1, enables Bank110 of the SRAM 14 1 read-write BNK110_EN_0 Disables Bank110 of the SRAM 0 BNK110_EN_1 Enables Bank110 of the SRAM 1 BNK111_EN When 1, enables Bank111 of the SRAM 15 1 read-write BNK111_EN_0 Disables Bank111 of the SRAM 0 BNK111_EN_1 Enables Bank111 of the SRAM 1 BNK112_EN When 1, enables Bank112 of the SRAM 16 1 read-write BNK112_EN_0 Disables Bank112 of the SRAM 0 BNK112_EN_1 Enables Bank112 of the SRAM 1 BNK113_EN When 1, enables Bank113 of the SRAM 17 1 read-write BNK113_EN_0 Disables Bank113 of the SRAM 0 BNK113_EN_1 Enables Bank113 of the SRAM 1 BNK114_EN When 1, enables Bank114 of the SRAM 18 1 read-write BNK114_EN_0 Disables Bank114 of the SRAM 0 BNK114_EN_1 Enables Bank114 of the SRAM 1 BNK115_EN When 1, enables Bank115 of the SRAM 19 1 read-write BNK115_EN_0 Disables Bank115 of the SRAM 0 BNK115_EN_1 Enables Bank115 of the SRAM 1 BNK116_EN When 1, enables Bank116 of the SRAM 20 1 read-write BNK116_EN_0 Disables Bank116 of the SRAM 0 BNK116_EN_1 Enables Bank116 of the SRAM 1 BNK117_EN When 1, enables Bank117 of the SRAM 21 1 read-write BNK117_EN_0 Disables Bank117 of the SRAM 0 BNK117_EN_1 Enables Bank117 of the SRAM 1 BNK118_EN When 1, enables Bank118 of the SRAM 22 1 read-write BNK118_EN_0 Disables Bank118 of the SRAM 0 BNK118_EN_1 Enables Bank118 of the SRAM 1 BNK119_EN When 1, enables Bank119 of the SRAM 23 1 read-write BNK119_EN_0 Disables Bank119 of the SRAM 0 BNK119_EN_1 Enables Bank119 of the SRAM 1 BNK120_EN When 1, enables Bank120 of the SRAM 24 1 read-write BNK120_EN_0 Disables Bank120 of the SRAM 0 BNK120_EN_1 Enables Bank120 of the SRAM 1 BNK121_EN When 1, enables Bank121 of the SRAM 25 1 read-write BNK121_EN_0 Disables Bank121 of the SRAM 0 BNK121_EN_1 Enables Bank121 of the SRAM 1 BNK122_EN When 1, enables Bank122 of the SRAM 26 1 read-write BNK122_EN_0 Disables Bank122 of the SRAM 0 BNK122_EN_1 Enables Bank122 of the SRAM 1 BNK123_EN When 1, enables Bank123 of the SRAM 27 1 read-write BNK123_EN_0 Disables Bank123 of the SRAM 0 BNK123_EN_1 Enables Bank123 of the SRAM 1 BNK124_EN When 1, enables Bank124 of the SRAM 28 1 read-write BNK124_EN_0 Disables Bank124 of the SRAM 0 BNK124_EN_1 Enables Bank124 of the SRAM 1 BNK125_EN When 1, enables Bank125 of the SRAM 29 1 read-write BNK125_EN_0 Disables Bank125 of the SRAM 0 BNK125_EN_1 Enables Bank125 of the SRAM 1 BNK126_EN When 1, enables Bank126 of the SRAM 30 1 read-write BNK126_EN_0 Disables Bank126 of the SRAM 0 BNK126_EN_1 Enables Bank126 of the SRAM 1 BNK127_EN When 1, enables Bank127 of the SRAM 31 1 read-write BNK127_EN_0 Disables Bank127 of the SRAM 0 BNK127_EN_1 Enables Bank127 of the SRAM 1 BNK96_EN When 1, enables Bank96 of the SRAM 0 1 read-write BNK96_EN_0 Disables Bank96 of the SRAM 0 BNK96_EN_1 Enables Bank96 of the SRAM 1 BNK97_EN When 1, enables Bank97 of the SRAM 1 1 read-write BNK97_EN_0 Disables Bank97 of the SRAM 0 BNK97_EN_1 Enables Bank97 of the SRAM 1 BNK98_EN When 1, enables Bank98 of the SRAM 2 1 read-write BNK98_EN_0 Disables Bank98 of the SRAM 0 BNK98_EN_1 Enables Bank98 of the SRAM 1 BNK99_EN When 1, enables Bank99 of the SRAM 3 1 read-write BNK99_EN_0 Disables Bank99 of the SRAM 0 BNK99_EN_1 Enables Bank99 of the SRAM 1 SYS_SRAM_BLKRET_CTL0 SRAM_BLKRET_CTL0 SRAM Block Retention Control Register 0 0x70 32 read-write n 0xFFFFFFFF 0xFFFFFFFF BLK0_EN Block0 is always retained in LPM3, LPM4 and LPM3.5 modes of operation 0 1 read-only BLK10_EN When 1, Block10 of the SRAM is retained in LPM3 and LPM4 10 1 read-write BLK10_EN_0 Block10 of the SRAM is not retained in LPM3 or LPM4 0 BLK10_EN_1 Block10 of the SRAM is retained in LPM3 and LPM4 1 BLK11_EN When 1, Block11 of the SRAM is retained in LPM3 and LPM4 11 1 read-write BLK11_EN_0 Block11 of the SRAM is not retained in LPM3 or LPM4 0 BLK11_EN_1 Block11 of the SRAM is retained in LPM3 and LPM4 1 BLK12_EN When 1, Block12 of the SRAM is retained in LPM3 and LPM4 12 1 read-write BLK12_EN_0 Block12 of the SRAM is not retained in LPM3 or LPM4 0 BLK12_EN_1 Block12 of the SRAM is retained in LPM3 and LPM4 1 BLK13_EN When 1, Block13 of the SRAM is retained in LPM3 and LPM4 13 1 read-write BLK13_EN_0 Block13 of the SRAM is not retained in LPM3 or LPM4 0 BLK13_EN_1 Block13 of the SRAM is retained in LPM3 and LPM4 1 BLK14_EN When 1, Block14 of the SRAM is retained in LPM3 and LPM4 14 1 read-write BLK14_EN_0 Block14 of the SRAM is not retained in LPM3 or LPM4 0 BLK14_EN_1 Block14 of the SRAM is retained in LPM3 and LPM4 1 BLK15_EN When 1, Block15 of the SRAM is retained in LPM3 and LPM4 15 1 read-write BLK15_EN_0 Block15 of the SRAM is not retained in LPM3 or LPM4 0 BLK15_EN_1 Block15 of the SRAM is retained in LPM3 and LPM4 1 BLK16_EN When 1, Block16 of the SRAM is retained in LPM3 and LPM4 16 1 read-write BLK16_EN_0 Block16 of the SRAM is not retained in LPM3 or LPM4 0 BLK16_EN_1 Block16 of the SRAM is retained in LPM3 and LPM4 1 BLK17_EN When 1, Block17 of the SRAM is retained in LPM3 and LPM4 17 1 read-write BLK17_EN_0 Block17 of the SRAM is not retained in LPM3 or LPM4 0 BLK17_EN_1 Block17 of the SRAM is retained in LPM3 and LPM4 1 BLK18_EN When 1, Block18 of the SRAM is retained in LPM3 and LPM4 18 1 read-write BLK18_EN_0 Block18 of the SRAM is not retained in LPM3 or LPM4 0 BLK18_EN_1 Block18 of the SRAM is retained in LPM3 and LPM4 1 BLK19_EN When 1, Block19 of the SRAM is retained in LPM3 and LPM4 19 1 read-write BLK19_EN_0 Block19 of the SRAM is not retained in LPM3 or LPM4 0 BLK19_EN_1 Block19 of the SRAM is retained in LPM3 and LPM4 1 BLK1_EN When 1, Block1 of the SRAM is retained in LPM3 and LPM4 1 1 read-write BLK1_EN_0 Block1 of the SRAM is not retained in LPM3 or LPM4 0 BLK1_EN_1 Block1 of the SRAM is retained in LPM3 and LPM4 1 BLK20_EN When 1, Block20 of the SRAM is retained in LPM3 and LPM4 20 1 read-write BLK20_EN_0 Block20 of the SRAM is not retained in LPM3 or LPM4 0 BLK20_EN_1 Block20 of the SRAM is retained in LPM3 and LPM4 1 BLK21_EN When 1, Block21 of the SRAM is retained in LPM3 and LPM4 21 1 read-write BLK21_EN_0 Block21 of the SRAM is not retained in LPM3 or LPM4 0 BLK21_EN_1 Block21 of the SRAM is retained in LPM3 and LPM4 1 BLK22_EN When 1, Block22 of the SRAM is retained in LPM3 and LPM4 22 1 read-write BLK22_EN_0 Block22 of the SRAM is not retained in LPM3 or LPM4 0 BLK22_EN_1 Block22 of the SRAM is retained in LPM3 and LPM4 1 BLK23_EN When 1, Block23 of the SRAM is retained in LPM3 and LPM4 23 1 read-write BLK23_EN_0 Block23 of the SRAM is not retained in LPM3 or LPM4 0 BLK23_EN_1 Block23 of the SRAM is retained in LPM3 and LPM4 1 BLK24_EN When 1, Block24 of the SRAM is retained in LPM3 and LPM4 24 1 read-write BLK24_EN_0 Block24 of the SRAM is not retained in LPM3 or LPM4 0 BLK24_EN_1 Block24 of the SRAM is retained in LPM3 and LPM4 1 BLK25_EN When 1, Block25 of the SRAM is retained in LPM3 and LPM4 25 1 read-write BLK25_EN_0 Block25 of the SRAM is not retained in LPM3 or LPM4 0 BLK25_EN_1 Block25 of the SRAM is retained in LPM3 and LPM4 1 BLK26_EN When 1, Block26 of the SRAM is retained in LPM3 and LPM4 26 1 read-write BLK26_EN_0 Block26 of the SRAM is not retained in LPM3 or LPM4 0 BLK26_EN_1 Block26 of the SRAM is retained in LPM3 and LPM4 1 BLK27_EN When 1, Block27 of the SRAM is retained in LPM3 and LPM4 27 1 read-write BLK27_EN_0 Block27 of the SRAM is not retained in LPM3 or LPM4 0 BLK27_EN_1 Block27 of the SRAM is retained in LPM3 and LPM4 1 BLK28_EN When 1, Block28 of the SRAM is retained in LPM3 and LPM4 28 1 read-write BLK28_EN_0 Block28 of the SRAM is not retained in LPM3 or LPM4 0 BLK28_EN_1 Block28 of the SRAM is retained in LPM3 and LPM4 1 BLK29_EN When 1, Block29 of the SRAM is retained in LPM3 and LPM4 29 1 read-write BLK29_EN_0 Block29 of the SRAM is not retained in LPM3 or LPM4 0 BLK29_EN_1 Block29 of the SRAM is retained in LPM3 and LPM4 1 BLK2_EN When 1, Block2 of the SRAM is retained in LPM3 and LPM4 2 1 read-write BLK2_EN_0 Block2 of the SRAM is not retained in LPM3 or LPM4 0 BLK2_EN_1 Block2 of the SRAM is retained in LPM3 and LPM4 1 BLK30_EN When 1, Block30 of the SRAM is retained in LPM3 and LPM4 30 1 read-write BLK30_EN_0 Block30 of the SRAM is not retained in LPM3 or LPM4 0 BLK30_EN_1 Block30 of the SRAM is retained in LPM3 and LPM4 1 BLK31_EN When 1, Block31 of the SRAM is retained in LPM3 and LPM4 31 1 read-write BLK31_EN_0 Block31 of the SRAM is not retained in LPM3 or LPM4 0 BLK31_EN_1 Block31 of the SRAM is retained in LPM3 and LPM4 1 BLK3_EN When 1, Block3 of the SRAM is retained in LPM3 and LPM4 3 1 read-write BLK3_EN_0 Block3 of the SRAM is not retained in LPM3 or LPM4 0 BLK3_EN_1 Block3 of the SRAM is retained in LPM3 and LPM4 1 BLK4_EN When 1, Block4 of the SRAM is retained in LPM3 and LPM4 4 1 read-write BLK4_EN_0 Block4 of the SRAM is not retained in LPM3 or LPM4 0 BLK4_EN_1 Block4 of the SRAM is retained in LPM3 and LPM4 1 BLK5_EN When 1, Block5 of the SRAM is retained in LPM3 and LPM4 5 1 read-write BLK5_EN_0 Block5 of the SRAM is not retained in LPM3 or LPM4 0 BLK5_EN_1 Block5 of the SRAM is retained in LPM3 and LPM4 1 BLK6_EN When 1, Block6 of the SRAM is retained in LPM3 and LPM4 6 1 read-write BLK6_EN_0 Block6 of the SRAM is not retained in LPM3 or LPM4 0 BLK6_EN_1 Block6 of the SRAM is retained in LPM3 and LPM4 1 BLK7_EN When 1, Block7 of the SRAM is retained in LPM3 and LPM4 7 1 read-write BLK7_EN_0 Block7 of the SRAM is not retained in LPM3 or LPM4 0 BLK7_EN_1 Block7 of the SRAM is retained in LPM3 and LPM4 1 BLK8_EN When 1, Block8 of the SRAM is retained in LPM3 and LPM4 8 1 read-write BLK8_EN_0 Block8 of the SRAM is not retained in LPM3 or LPM4 0 BLK8_EN_1 Block8 of the SRAM is retained in LPM3 and LPM4 1 BLK9_EN When 1, Block9 of the SRAM is retained in LPM3 and LPM4 9 1 read-write BLK9_EN_0 Block9 of the SRAM is not retained in LPM3 or LPM4 0 BLK9_EN_1 Block9 of the SRAM is retained in LPM3 and LPM4 1 SYS_SRAM_BLKRET_CTL1 SRAM_BLKRET_CTL1 SRAM Block Retention Control Register 1 0x74 32 read-write n 0xFFFFFFFF 0xFFFFFFFF BLK32_EN When 1, Block32 of the SRAM is retained in LPM3 and LPM4 0 1 read-write BLK32_EN_0 Block32 of the SRAM is not retained in LPM3 or LPM4 0 BLK32_EN_1 Block32 of the SRAM is retained in LPM3 and LPM4 1 BLK33_EN When 1, Block33 of the SRAM is retained in LPM3 and LPM4 1 1 read-write BLK33_EN_0 Block33 of the SRAM is not retained in LPM3 or LPM4 0 BLK33_EN_1 Block33 of the SRAM is retained in LPM3 and LPM4 1 BLK34_EN When 1, Block34 of the SRAM is retained in LPM3 and LPM4 2 1 read-write BLK34_EN_0 Block34 of the SRAM is not retained in LPM3 or LPM4 0 BLK34_EN_1 Block34 of the SRAM is retained in LPM3 and LPM4 1 BLK35_EN When 1, Block35 of the SRAM is retained in LPM3 and LPM4 3 1 read-write BLK35_EN_0 Block35 of the SRAM is not retained in LPM3 or LPM4 0 BLK35_EN_1 Block35 of the SRAM is retained in LPM3 and LPM4 1 BLK36_EN When 1, Block36 of the SRAM is retained in LPM3 and LPM4 4 1 read-write BLK36_EN_0 Block36 of the SRAM is not retained in LPM3 or LPM4 0 BLK36_EN_1 Block36 of the SRAM is retained in LPM3 and LPM4 1 BLK37_EN When 1, Block37 of the SRAM is retained in LPM3 and LPM4 5 1 read-write BLK37_EN_0 Block37 of the SRAM is not retained in LPM3 or LPM4 0 BLK37_EN_1 Block37 of the SRAM is retained in LPM3 and LPM4 1 BLK38_EN When 1, Block38 of the SRAM is retained in LPM3 and LPM4 6 1 read-write BLK38_EN_0 Block38 of the SRAM is not retained in LPM3 or LPM4 0 BLK38_EN_1 Block38 of the SRAM is retained in LPM3 and LPM4 1 BLK39_EN When 1, Block39 of the SRAM is retained in LPM3 and LPM4 7 1 read-write BLK39_EN_0 Block39 of the SRAM is not retained in LPM3 or LPM4 0 BLK39_EN_1 Block39 of the SRAM is retained in LPM3 and LPM4 1 BLK40_EN When 1, Block40 of the SRAM is retained in LPM3 and LPM4 8 1 read-write BLK40_EN_0 Block40 of the SRAM is not retained in LPM3 or LPM4 0 BLK40_EN_1 Block40 of the SRAM is retained in LPM3 and LPM4 1 BLK41_EN When 1, Block41 of the SRAM is retained in LPM3 and LPM4 9 1 read-write BLK41_EN_0 Block41 of the SRAM is not retained in LPM3 or LPM4 0 BLK41_EN_1 Block41 of the SRAM is retained in LPM3 and LPM4 1 BLK42_EN When 1, Block42 of the SRAM is retained in LPM3 and LPM4 10 1 read-write BLK42_EN_0 Block42 of the SRAM is not retained in LPM3 or LPM4 0 BLK42_EN_1 Block42 of the SRAM is retained in LPM3 and LPM4 1 BLK43_EN When 1, Block43 of the SRAM is retained in LPM3 and LPM4 11 1 read-write BLK43_EN_0 Block43 of the SRAM is not retained in LPM3 or LPM4 0 BLK43_EN_1 Block43 of the SRAM is retained in LPM3 and LPM4 1 BLK44_EN When 1, Block44 of the SRAM is retained in LPM3 and LPM4 12 1 read-write BLK44_EN_0 Block44 of the SRAM is not retained in LPM3 or LPM4 0 BLK44_EN_1 Block44 of the SRAM is retained in LPM3 and LPM4 1 BLK45_EN When 1, Block45 of the SRAM is retained in LPM3 and LPM4 13 1 read-write BLK45_EN_0 Block45 of the SRAM is not retained in LPM3 or LPM4 0 BLK45_EN_1 Block45 of the SRAM is retained in LPM3 and LPM4 1 BLK46_EN When 1, Block46 of the SRAM is retained in LPM3 and LPM4 14 1 read-write BLK46_EN_0 Block46 of the SRAM is not retained in LPM3 or LPM4 0 BLK46_EN_1 Block46 of the SRAM is retained in LPM3 and LPM4 1 BLK47_EN When 1, Block47 of the SRAM is retained in LPM3 and LPM4 15 1 read-write BLK47_EN_0 Block47 of the SRAM is not retained in LPM3 or LPM4 0 BLK47_EN_1 Block47 of the SRAM is retained in LPM3 and LPM4 1 BLK48_EN When 1, Block48 of the SRAM is retained in LPM3 and LPM4 16 1 read-write BLK48_EN_0 Block48 of the SRAM is not retained in LPM3 or LPM4 0 BLK48_EN_1 Block48 of the SRAM is retained in LPM3 and LPM4 1 BLK49_EN When 1, Block49 of the SRAM is retained in LPM3 and LPM4 17 1 read-write BLK49_EN_0 Block49 of the SRAM is not retained in LPM3 or LPM4 0 BLK49_EN_1 Block49 of the SRAM is retained in LPM3 and LPM4 1 BLK50_EN When 1, Block50 of the SRAM is retained in LPM3 and LPM4 18 1 read-write BLK50_EN_0 Block50 of the SRAM is not retained in LPM3 or LPM4 0 BLK50_EN_1 Block50 of the SRAM is retained in LPM3 and LPM4 1 BLK51_EN When 1, Block51 of the SRAM is retained in LPM3 and LPM4 19 1 read-write BLK51_EN_0 Block51 of the SRAM is not retained in LPM3 or LPM4 0 BLK51_EN_1 Block51 of the SRAM is retained in LPM3 and LPM4 1 BLK52_EN When 1, Block52 of the SRAM is retained in LPM3 and LPM4 20 1 read-write BLK52_EN_0 Block52 of the SRAM is not retained in LPM3 or LPM4 0 BLK52_EN_1 Block52 of the SRAM is retained in LPM3 and LPM4 1 BLK53_EN When 1, Block53 of the SRAM is retained in LPM3 and LPM4 21 1 read-write BLK53_EN_0 Block53 of the SRAM is not retained in LPM3 or LPM4 0 BLK53_EN_1 Block53 of the SRAM is retained in LPM3 and LPM4 1 BLK54_EN When 1, Block54 of the SRAM is retained in LPM3 and LPM4 22 1 read-write BLK54_EN_0 Block54 of the SRAM is not retained in LPM3 or LPM4 0 BLK54_EN_1 Block54 of the SRAM is retained in LPM3 and LPM4 1 BLK55_EN When 1, Block55 of the SRAM is retained in LPM3 and LPM4 23 1 read-write BLK55_EN_0 Block55 of the SRAM is not retained in LPM3 or LPM4 0 BLK55_EN_1 Block55 of the SRAM is retained in LPM3 and LPM4 1 BLK56_EN When 1, Block56 of the SRAM is retained in LPM3 and LPM4 24 1 read-write BLK56_EN_0 Block56 of the SRAM is not retained in LPM3 or LPM4 0 BLK56_EN_1 Block56 of the SRAM is retained in LPM3 and LPM4 1 BLK57_EN When 1, Block57 of the SRAM is retained in LPM3 and LPM4 25 1 read-write BLK57_EN_0 Block57 of the SRAM is not retained in LPM3 or LPM4 0 BLK57_EN_1 Block57 of the SRAM is retained in LPM3 and LPM4 1 BLK58_EN When 1, Block58 of the SRAM is retained in LPM3 and LPM4 26 1 read-write BLK58_EN_0 Block58 of the SRAM is not retained in LPM3 or LPM4 0 BLK58_EN_1 Block58 of the SRAM is retained in LPM3 and LPM4 1 BLK59_EN When 1, Block59 of the SRAM is retained in LPM3 and LPM4 27 1 read-write BLK59_EN_0 Block59 of the SRAM is not retained in LPM3 or LPM4 0 BLK59_EN_1 Block59 of the SRAM is retained in LPM3 and LPM4 1 BLK60_EN When 1, Block60 of the SRAM is retained in LPM3 and LPM4 28 1 read-write BLK60_EN_0 Block60 of the SRAM is not retained in LPM3 or LPM4 0 BLK60_EN_1 Block60 of the SRAM is retained in LPM3 and LPM4 1 BLK61_EN When 1, Block61 of the SRAM is retained in LPM3 and LPM4 29 1 read-write BLK61_EN_0 Block61 of the SRAM is not retained in LPM3 or LPM4 0 BLK61_EN_1 Block61 of the SRAM is retained in LPM3 and LPM4 1 BLK62_EN When 1, Block62 of the SRAM is retained in LPM3 and LPM4 30 1 read-write BLK62_EN_0 Block62 of the SRAM is not retained in LPM3 or LPM4 0 BLK62_EN_1 Block62 of the SRAM is retained in LPM3 and LPM4 1 BLK63_EN When 1, Block63 of the SRAM is retained in LPM3 and LPM4 31 1 read-write BLK63_EN_0 Block63 of the SRAM is not retained in LPM3 or LPM4 0 BLK63_EN_1 Block63 of the SRAM is retained in LPM3 and LPM4 1 SYS_SRAM_BLKRET_CTL2 SRAM_BLKRET_CTL2 SRAM Block Retention Control Register 2 0x78 32 read-write n 0xFFFFFFFF 0xFFFFFFFF BLK64_EN When 1, Block64 of the SRAM is retained in LPM3 and LPM4 0 1 read-write BLK64_EN_0 Block64 of the SRAM is not retained in LPM3 or LPM4 0 BLK64_EN_1 Block64 of the SRAM is retained in LPM3 and LPM4 1 BLK65_EN When 1, Block65 of the SRAM is retained in LPM3 and LPM4 1 1 read-write BLK65_EN_0 Block65 of the SRAM is not retained in LPM3 or LPM4 0 BLK65_EN_1 Block65 of the SRAM is retained in LPM3 and LPM4 1 BLK66_EN When 1, Block66 of the SRAM is retained in LPM3 and LPM4 2 1 read-write BLK66_EN_0 Block66 of the SRAM is not retained in LPM3 or LPM4 0 BLK66_EN_1 Block66 of the SRAM is retained in LPM3 and LPM4 1 BLK67_EN When 1, Block67 of the SRAM is retained in LPM3 and LPM4 3 1 read-write BLK67_EN_0 Block67 of the SRAM is not retained in LPM3 or LPM4 0 BLK67_EN_1 Block67 of the SRAM is retained in LPM3 and LPM4 1 BLK68_EN When 1, Block68 of the SRAM is retained in LPM3 and LPM4 4 1 read-write BLK68_EN_0 Block68 of the SRAM is not retained in LPM3 or LPM4 0 BLK68_EN_1 Block68 of the SRAM is retained in LPM3 and LPM4 1 BLK69_EN When 1, Block69 of the SRAM is retained in LPM3 and LPM4 5 1 read-write BLK69_EN_0 Block69 of the SRAM is not retained in LPM3 or LPM4 0 BLK69_EN_1 Block69 of the SRAM is retained in LPM3 and LPM4 1 BLK70_EN When 1, Block70 of the SRAM is retained in LPM3 and LPM4 6 1 read-write BLK70_EN_0 Block70 of the SRAM is not retained in LPM3 or LPM4 0 BLK70_EN_1 Block70 of the SRAM is retained in LPM3 and LPM4 1 BLK71_EN When 1, Block71 of the SRAM is retained in LPM3 and LPM4 7 1 read-write BLK71_EN_0 Block71 of the SRAM is not retained in LPM3 or LPM4 0 BLK71_EN_1 Block71 of the SRAM is retained in LPM3 and LPM4 1 BLK72_EN When 1, Block72 of the SRAM is retained in LPM3 and LPM4 8 1 read-write BLK72_EN_0 Block72 of the SRAM is not retained in LPM3 or LPM4 0 BLK72_EN_1 Block72 of the SRAM is retained in LPM3 and LPM4 1 BLK73_EN When 1, Block73 of the SRAM is retained in LPM3 and LPM4 9 1 read-write BLK73_EN_0 Block73 of the SRAM is not retained in LPM3 or LPM4 0 BLK73_EN_1 Block73 of the SRAM is retained in LPM3 and LPM4 1 BLK74_EN When 1, Block74 of the SRAM is retained in LPM3 and LPM4 10 1 read-write BLK74_EN_0 Block74 of the SRAM is not retained in LPM3 or LPM4 0 BLK74_EN_1 Block74 of the SRAM is retained in LPM3 and LPM4 1 BLK75_EN When 1, Block75 of the SRAM is retained in LPM3 and LPM4 11 1 read-write BLK75_EN_0 Block75 of the SRAM is not retained in LPM3 or LPM4 0 BLK75_EN_1 Block75 of the SRAM is retained in LPM3 and LPM4 1 BLK76_EN When 1, Block76 of the SRAM is retained in LPM3 and LPM4 12 1 read-write BLK76_EN_0 Block76 of the SRAM is not retained in LPM3 or LPM4 0 BLK76_EN_1 Block76 of the SRAM is retained in LPM3 and LPM4 1 BLK77_EN When 1, Block77 of the SRAM is retained in LPM3 and LPM4 13 1 read-write BLK77_EN_0 Block77 of the SRAM is not retained in LPM3 or LPM4 0 BLK77_EN_1 Block77 of the SRAM is retained in LPM3 and LPM4 1 BLK78_EN When 1, Block78 of the SRAM is retained in LPM3 and LPM4 14 1 read-write BLK78_EN_0 Block78 of the SRAM is not retained in LPM3 or LPM4 0 BLK78_EN_1 Block78 of the SRAM is retained in LPM3 and LPM4 1 BLK79_EN When 1, Block79 of the SRAM is retained in LPM3 and LPM4 15 1 read-write BLK79_EN_0 Block79 of the SRAM is not retained in LPM3 or LPM4 0 BLK79_EN_1 Block79 of the SRAM is retained in LPM3 and LPM4 1 BLK80_EN When 1, Block80 of the SRAM is retained in LPM3 and LPM4 16 1 read-write BLK80_EN_0 Block80 of the SRAM is not retained in LPM3 or LPM4 0 BLK80_EN_1 Block80 of the SRAM is retained in LPM3 and LPM4 1 BLK81_EN When 1, Block81 of the SRAM is retained in LPM3 and LPM4 17 1 read-write BLK81_EN_0 Block81 of the SRAM is not retained in LPM3 or LPM4 0 BLK81_EN_1 Block81 of the SRAM is retained in LPM3 and LPM4 1 BLK82_EN When 1, Block82 of the SRAM is retained in LPM3 and LPM4 18 1 read-write BLK82_EN_0 Block82 of the SRAM is not retained in LPM3 or LPM4 0 BLK82_EN_1 Block82 of the SRAM is retained in LPM3 and LPM4 1 BLK83_EN When 1, Block83 of the SRAM is retained in LPM3 and LPM4 19 1 read-write BLK83_EN_0 Block83 of the SRAM is not retained in LPM3 or LPM4 0 BLK83_EN_1 Block83 of the SRAM is retained in LPM3 and LPM4 1 BLK84_EN When 1, Block84 of the SRAM is retained in LPM3 and LPM4 20 1 read-write BLK84_EN_0 Block84 of the SRAM is not retained in LPM3 or LPM4 0 BLK84_EN_1 Block84 of the SRAM is retained in LPM3 and LPM4 1 BLK85_EN When 1, Block85 of the SRAM is retained in LPM3 and LPM4 21 1 read-write BLK85_EN_0 Block85 of the SRAM is not retained in LPM3 or LPM4 0 BLK85_EN_1 Block85 of the SRAM is retained in LPM3 and LPM4 1 BLK86_EN When 1, Block86 of the SRAM is retained in LPM3 and LPM4 22 1 read-write BLK86_EN_0 Block86 of the SRAM is not retained in LPM3 or LPM4 0 BLK86_EN_1 Block86 of the SRAM is retained in LPM3 and LPM4 1 BLK87_EN When 1, Block87 of the SRAM is retained in LPM3 and LPM4 23 1 read-write BLK87_EN_0 Block87 of the SRAM is not retained in LPM3 or LPM4 0 BLK87_EN_1 Block87 of the SRAM is retained in LPM3 and LPM4 1 BLK88_EN When 1, Block88 of the SRAM is retained in LPM3 and LPM4 24 1 read-write BLK88_EN_0 Block88 of the SRAM is not retained in LPM3 or LPM4 0 BLK88_EN_1 Block88 of the SRAM is retained in LPM3 and LPM4 1 BLK89_EN When 1, Block89 of the SRAM is retained in LPM3 and LPM4 25 1 read-write BLK89_EN_0 Block89 of the SRAM is not retained in LPM3 or LPM4 0 BLK89_EN_1 Block89 of the SRAM is retained in LPM3 and LPM4 1 BLK90_EN When 1, Block90 of the SRAM is retained in LPM3 and LPM4 26 1 read-write BLK90_EN_0 Block90 of the SRAM is not retained in LPM3 or LPM4 0 BLK90_EN_1 Block90 of the SRAM is retained in LPM3 and LPM4 1 BLK91_EN When 1, Block91 of the SRAM is retained in LPM3 and LPM4 27 1 read-write BLK91_EN_0 Block91 of the SRAM is not retained in LPM3 or LPM4 0 BLK91_EN_1 Block91 of the SRAM is retained in LPM3 and LPM4 1 BLK92_EN When 1, Block92 of the SRAM is retained in LPM3 and LPM4 28 1 read-write BLK92_EN_0 Block92 of the SRAM is not retained in LPM3 or LPM4 0 BLK92_EN_1 Block92 of the SRAM is retained in LPM3 and LPM4 1 BLK93_EN When 1, Block93 of the SRAM is retained in LPM3 and LPM4 29 1 read-write BLK93_EN_0 Block93 of the SRAM is not retained in LPM3 or LPM4 0 BLK93_EN_1 Block93 of the SRAM is retained in LPM3 and LPM4 1 BLK94_EN When 1, Block94 of the SRAM is retained in LPM3 and LPM4 30 1 read-write BLK94_EN_0 Block94 of the SRAM is not retained in LPM3 or LPM4 0 BLK94_EN_1 Block94 of the SRAM is retained in LPM3 and LPM4 1 BLK95_EN When 1, Block95 of the SRAM is retained in LPM3 and LPM4 31 1 read-write BLK95_EN_0 Block95 of the SRAM is not retained in LPM3 or LPM4 0 BLK95_EN_1 Block95 of the SRAM is retained in LPM3 and LPM4 1 SYS_SRAM_BLKRET_CTL3 SRAM_BLKRET_CTL3 SRAM Block Retention Control Register 3 0x7C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF BLK100_EN When 1, Block100 of the SRAM is retained in LPM3 and LPM4 4 1 read-write BLK100_EN_0 Block100 of the SRAM is not retained in LPM3 or LPM4 0 BLK100_EN_1 Block100 of the SRAM is retained in LPM3 and LPM4 1 BLK101_EN When 1, Block101 of the SRAM is retained in LPM3 and LPM4 5 1 read-write BLK101_EN_0 Block101 of the SRAM is not retained in LPM3 or LPM4 0 BLK101_EN_1 Block101 of the SRAM is retained in LPM3 and LPM4 1 BLK102_EN When 1, Block102 of the SRAM is retained in LPM3 and LPM4 6 1 read-write BLK102_EN_0 Block102 of the SRAM is not retained in LPM3 or LPM4 0 BLK102_EN_1 Block102 of the SRAM is retained in LPM3 and LPM4 1 BLK103_EN When 1, Block103 of the SRAM is retained in LPM3 and LPM4 7 1 read-write BLK103_EN_0 Block103 of the SRAM is not retained in LPM3 or LPM4 0 BLK103_EN_1 Block103 of the SRAM is retained in LPM3 and LPM4 1 BLK104_EN When 1, Block104 of the SRAM is retained in LPM3 and LPM4 8 1 read-write BLK104_EN_0 Block104 of the SRAM is not retained in LPM3 or LPM4 0 BLK104_EN_1 Block104 of the SRAM is retained in LPM3 and LPM4 1 BLK105_EN When 1, Block105 of the SRAM is retained in LPM3 and LPM4 9 1 read-write BLK105_EN_0 Block105 of the SRAM is not retained in LPM3 or LPM4 0 BLK105_EN_1 Block105 of the SRAM is retained in LPM3 and LPM4 1 BLK106_EN When 1, Block106 of the SRAM is retained in LPM3 and LPM4 10 1 read-write BLK106_EN_0 Block106 of the SRAM is not retained in LPM3 or LPM4 0 BLK106_EN_1 Block106 of the SRAM is retained in LPM3 and LPM4 1 BLK107_EN When 1, Block107 of the SRAM is retained in LPM3 and LPM4 11 1 read-write BLK107_EN_0 Block107 of the SRAM is not retained in LPM3 or LPM4 0 BLK107_EN_1 Block107 of the SRAM is retained in LPM3 and LPM4 1 BLK108_EN When 1, Block108 of the SRAM is retained in LPM3 and LPM4 12 1 read-write BLK108_EN_0 Block108 of the SRAM is not retained in LPM3 or LPM4 0 BLK108_EN_1 Block108 of the SRAM is retained in LPM3 and LPM4 1 BLK109_EN When 1, Block109 of the SRAM is retained in LPM3 and LPM4 13 1 read-write BLK109_EN_0 Block109 of the SRAM is not retained in LPM3 or LPM4 0 BLK109_EN_1 Block109 of the SRAM is retained in LPM3 and LPM4 1 BLK110_EN When 1, Block110 of the SRAM is retained in LPM3 and LPM4 14 1 read-write BLK110_EN_0 Block110 of the SRAM is not retained in LPM3 or LPM4 0 BLK110_EN_1 Block110 of the SRAM is retained in LPM3 and LPM4 1 BLK111_EN When 1, Block111 of the SRAM is retained in LPM3 and LPM4 15 1 read-write BLK111_EN_0 Block111 of the SRAM is not retained in LPM3 or LPM4 0 BLK111_EN_1 Block111 of the SRAM is retained in LPM3 and LPM4 1 BLK112_EN When 1, Block112 of the SRAM is retained in LPM3 and LPM4 16 1 read-write BLK112_EN_0 Block112 of the SRAM is not retained in LPM3 or LPM4 0 BLK112_EN_1 Block112 of the SRAM is retained in LPM3 and LPM4 1 BLK113_EN When 1, Block113 of the SRAM is retained in LPM3 and LPM4 17 1 read-write BLK113_EN_0 Block113 of the SRAM is not retained in LPM3 or LPM4 0 BLK113_EN_1 Block113 of the SRAM is retained in LPM3 and LPM4 1 BLK114_EN When 1, Block114 of the SRAM is retained in LPM3 and LPM4 18 1 read-write BLK114_EN_0 Block114 of the SRAM is not retained in LPM3 or LPM4 0 BLK114_EN_1 Block114 of the SRAM is retained in LPM3 and LPM4 1 BLK115_EN When 1, Block115 of the SRAM is retained in LPM3 and LPM4 19 1 read-write BLK115_EN_0 Block115 of the SRAM is not retained in LPM3 or LPM4 0 BLK115_EN_1 Block115 of the SRAM is retained in LPM3 and LPM4 1 BLK116_EN When 1, Block116 of the SRAM is retained in LPM3 and LPM4 20 1 read-write BLK116_EN_0 Block116 of the SRAM is not retained in LPM3 or LPM4 0 BLK116_EN_1 Block116 of the SRAM is retained in LPM3 and LPM4 1 BLK117_EN When 1, Block117 of the SRAM is retained in LPM3 and LPM4 21 1 read-write BLK117_EN_0 Block117 of the SRAM is not retained in LPM3 or LPM4 0 BLK117_EN_1 Block117 of the SRAM is retained in LPM3 and LPM4 1 BLK118_EN When 1, Block118 of the SRAM is retained in LPM3 and LPM4 22 1 read-write BLK118_EN_0 Block118 of the SRAM is not retained in LPM3 or LPM4 0 BLK118_EN_1 Block118 of the SRAM is retained in LPM3 and LPM4 1 BLK119_EN When 1, Block119 of the SRAM is retained in LPM3 and LPM4 23 1 read-write BLK119_EN_0 Block119 of the SRAM is not retained in LPM3 or LPM4 0 BLK119_EN_1 Block119 of the SRAM is retained in LPM3 and LPM4 1 BLK120_EN When 1, Block120 of the SRAM is retained in LPM3 and LPM4 24 1 read-write BLK120_EN_0 Block120 of the SRAM is not retained in LPM3 or LPM4 0 BLK120_EN_1 Block120 of the SRAM is retained in LPM3 and LPM4 1 BLK121_EN When 1, Block121 of the SRAM is retained in LPM3 and LPM4 25 1 read-write BLK121_EN_0 Block121 of the SRAM is not retained in LPM3 or LPM4 0 BLK121_EN_1 Block121 of the SRAM is retained in LPM3 and LPM4 1 BLK122_EN When 1, Block122 of the SRAM is retained in LPM3 and LPM4 26 1 read-write BLK122_EN_0 Block122 of the SRAM is not retained in LPM3 or LPM4 0 BLK122_EN_1 Block122 of the SRAM is retained in LPM3 and LPM4 1 BLK123_EN When 1, Block123 of the SRAM is retained in LPM3 and LPM4 27 1 read-write BLK123_EN_0 Block123 of the SRAM is not retained in LPM3 or LPM4 0 BLK123_EN_1 Block123 of the SRAM is retained in LPM3 and LPM4 1 BLK124_EN When 1, Block124 of the SRAM is retained in LPM3 and LPM4 28 1 read-write BLK124_EN_0 Block124 of the SRAM is not retained in LPM3 or LPM4 0 BLK124_EN_1 Block124 of the SRAM is retained in LPM3 and LPM4 1 BLK125_EN When 1, Block125 of the SRAM is retained in LPM3 and LPM4 29 1 read-write BLK125_EN_0 Block125 of the SRAM is not retained in LPM3 or LPM4 0 BLK125_EN_1 Block125 of the SRAM is retained in LPM3 and LPM4 1 BLK126_EN When 1, Block126 of the SRAM is retained in LPM3 and LPM4 30 1 read-write BLK126_EN_0 Block126 of the SRAM is not retained in LPM3 or LPM4 0 BLK126_EN_1 Block126 of the SRAM is retained in LPM3 and LPM4 1 BLK127_EN When 1, Block127 of the SRAM is retained in LPM3 and LPM4 31 1 read-write BLK127_EN_0 Block127 of the SRAM is not retained in LPM3 or LPM4 0 BLK127_EN_1 Block127 of the SRAM is retained in LPM3 and LPM4 1 BLK96_EN When 1, Block96 of the SRAM is retained in LPM3 and LPM4 0 1 read-write BLK96_EN_0 Block96 of the SRAM is not retained in LPM3 or LPM4 0 BLK96_EN_1 Block96 of the SRAM is retained in LPM3 and LPM4 1 BLK97_EN When 1, Block97 of the SRAM is retained in LPM3 and LPM4 1 1 read-write BLK97_EN_0 Block97 of the SRAM is not retained in LPM3 or LPM4 0 BLK97_EN_1 Block97 of the SRAM is retained in LPM3 and LPM4 1 BLK98_EN When 1, Block98 of the SRAM is retained in LPM3 and LPM4 2 1 read-write BLK98_EN_0 Block98 of the SRAM is not retained in LPM3 or LPM4 0 BLK98_EN_1 Block98 of the SRAM is retained in LPM3 and LPM4 1 BLK99_EN When 1, Block99 of the SRAM is retained in LPM3 and LPM4 3 1 read-write BLK99_EN_0 Block99 of the SRAM is not retained in LPM3 or LPM4 0 BLK99_EN_1 Block99 of the SRAM is retained in LPM3 and LPM4 1 SYS_SRAM_NUMBANKS SRAM_NUMBANKS SRAM Number of Banks Register 0x14 32 read-only n 0x0 0x0 NUM Indicates the number of SRAM banks on the device. 0 32 read-only SYS_SRAM_NUMBLOCKS SRAM_NUMBLOCKS SRAM Number of Blocks Register 0x18 32 read-only n 0x0 0x0 NUM Indicates the number of SRAM blocks on the device. 0 32 read-only SYS_SRAM_SIZE SRAM_SIZE SRAM Size Register 0x10 32 read-only n 0x0 0x0 SIZE Indicates the size of SRAM on the device 0 32 read-only SYS_SRAM_STAT SRAM_STAT SRAM Status Register 0x90 32 read-only n 0x0 0x0 BLKRET_RDY When 1, indicates SRAM is ready for access and blocks can be enabled/disabled for retention. 1 1 read-only BLKRET_RDY_enum_read read BLKRET_RDY_0 SRAM blocks are being set up for retention. Entry into LPM3, LPM4 should not be attempted until this bit is set to 1 0 BLKRET_RDY_1 SRAM is ready for accesses. All SRAM blocks are enabled/disabled for retention according to values of registers SYS_SRAM_BLKRET_CTLx (x = 0,1,2,3) 1 BNKEN_RDY When 1, indicates SRAM is ready for access and banks can be enabled/disabled. 0 1 read-only BNKEN_RDY_enum_read read BNKEN_RDY_0 SRAM is not ready for accesses. Banks are undergoing an enable or disable sequence, and reads or writes to SRAM are stalled until the banks are ready. 0 BNKEN_RDY_1 SRAM is ready for accesses. All SRAM banks are enabled/disabled according to values of registers SYS_SRAM_BANKEN_CTLx (x=0,1,2,3) 1 SYS_SYSTEM_STAT SYSTEM_STAT System Status Register 0x1020 32 read-only n 0x0 0x0 DBG_SEC_ACT Debug Security active 3 1 read-only IP_PROT_ACT Indicates if IP protection is active 5 1 read-only JTAG_SWD_LOCK_ACT Indicates if JTAG and SWD Lock is active 4 1 read-only SYS_WDTRESET_CTL WDTRESET_CTL Watchdog Reset Control Register 0x8 32 read-write n 0x3 0xFFFFFFFF TIMEOUT WDT timeout reset type 0 1 read-write TIMEOUT_0 WDT timeout event generates Soft reset 0 TIMEOUT_1 WDT timeout event generates Hard reset 1 VIOLATION WDT password violation reset type 1 1 read-write VIOLATION_0 WDT password violation event generates Soft reset 0 VIOLATION_1 WDT password violation event generates Hard reset 1 SystemControlSpace System Control Space for ARM core: SCnSCB, SCB, SysTick, NVIC, CoreDebug, MPU, FPU SystemControlSpace 0xE000E000 0x0 0x1000 registers n FPU_IRQ FPU Interrupt 4 ACTLR ACTLR Auxiliary Control Register 0x8 32 read-write n 0x0 0x0 DISDEFWBUF Disables write buffer us during default memorty map accesses. This causes all bus faults to be precise bus faults but decreases the performance of the processor because the stores to memory have to complete before the next instruction can be executed. 1 1 read-write DISFOLD Disables IT folding. 2 1 read-write DISFPCA Disable automatic update of CONTROL.FPCA 8 1 read-write DISMCYCINT Disables interruption of multi-cycle instructions. This increases the interrupt latency of the processor becuase LDM/STM completes before interrupt stacking occurs. 0 1 read-write DISOOFP Disables floating point instructions completing out of order with respect to integer instructions. 9 1 read-write AFR0 AFR0 Auxiliary Feature register0 0xD4C 32 read-only n 0x0 0x0 AFSR AFSR Auxiliary Fault Status Register 0xD3C 32 read-write n 0x0 0x0 IMPDEF Implementation defined. The bits map directly onto the signal assignment to the AUXFAULT inputs. 0 32 read-write AIRCR AIRCR Application Interrupt/Reset Control Register 0xD0C 32 read-write n 0xFA050000 0xFFFF7FFF ENDIANESS Data endianness bit. ENDIANNESS is sampled from the BIGEND input port during reset. You cannot change ENDIANNESS outside of reset. 15 1 read-only en_0b0 little endian 0 en_0b1 big endian 1 PRIGROUP Interrupt priority grouping field. The PRIGROUP field is a binary point position indicator for creating subpriorities for exceptions that share the same pre-emption level. It divides the PRI_n field in the Interrupt Priority Register into a pre-emption level and a subpriority level. The binary point is a left-of value. This means that the PRIGROUP value represents a point starting at the left of the Least Significant Bit (LSB). This is bit [0] of 7:0. The lowest value might not be 0 depending on the number of bits allocated for priorities, and implementation choices 8 3 read-write SYSRESETREQ Causes a signal to be asserted to the outer system that indicates a reset is requested. Intended to force a large system reset of all major components except for debug. Setting this bit does not prevent Halting Debug from running. 2 1 write-only VECTCLRACTIVE Clears all active state information for active NMI, fault, and interrupts. It is the responsibility of the application to reinitialize the stack. The VECTCLRACTIVE bit is for returning to a known state during debug. The VECTCLRACTIVE bit self-clears. IPSR is not cleared by this operation. So, if used by an application, it must only be used at the base level of activation, or within a system handler whose active bit can be set. 1 1 write-only VECTKEY Register key. Writing to this register requires 0x5FA in the VECTKEY field. Otherwise the write value is ignored. 16 16 write-only VECTRESET System Reset bit. Resets the system, with the exception of debug components. The VECTRESET bit self-clears. Reset clears the VECTRESET bit. For debugging, only write this bit when the core is halted. 0 1 write-only BFAR BFAR Bus Fault Address Register 0xD38 32 read-write n 0x0 0x0 ADDRESS Bus fault address field. ADDRESS is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the address requested by the instruction, even if that is not the address that faulted. Flags in the Bus Fault Status Register indicate the cause of the fault 0 32 read-write CCR CCR Configuration Control Register 0xD14 32 read-write n 0x200 0x0 BFHFNMIGN When enabled, this causes handlers running at priority -1 and -2 (Hard Fault, NMI, and FAULTMASK escalated handlers) to ignore Data Bus faults caused by load and store instructions. When disabled, these bus faults cause a lock-up. You must only use this enable with extreme caution. All data bus faults are ignored therefore you must only use it when the handler and its data are in absolutely safe memory. Its normal use is to probe system devices and bridges to detect control path problems and fix them. 8 1 read-write DIV_0_TRP Trap on Divide by 0. This enables faulting/halting when an attempt is made to divide by 0. The relevant Usage Fault Status Register bit is DIVBYZERO. 4 1 read-write NONBASETHREDENA When 0, default, It is only possible to enter Thread mode when returning from the last exception. When set to 1, Thread mode can be entered from any level in Handler mode by controlled return value. 0 1 read-write STKALIGN Stack alignment bit. 9 1 read-write en_0b0 Only 4-byte alignment is guaranteed for the SP used prior to the exception on exception entry. 0 en_0b1 On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned and the context to restore it is saved. The SP is restored on the associated exception return. 1 UNALIGN_TRP Trap for unaligned access. This enables faulting/halting on any unaligned half or full word access. Unaligned load-store multiples always fault. The relevant Usage Fault Status Register bit is UNALIGNED. 3 1 read-write USERSETMPEND If written as 1, enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception, which is one associated with the Main stack pointer. 1 1 read-write CFSR CFSR Configurable Fault Status Registers 0xD28 32 read-write n 0x0 0x0 BFARVALID This bit is set if the Bus Fault Address Register (BFAR) contains a valid address. This is true after a bus fault where the address is known. Other faults can clear this bit, such as a Mem Manage fault occurring later. If a Bus fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems if returning to a stacked active Bus fault handler whose BFAR value has been overwritten. 15 1 read-write DACCVIOL Data access violation flag. Attempting to load or store at a location that does not permit the operation sets the DACCVIOL flag. The return PC points to the faulting instruction. This error loads MMAR with the address of the attempted access. 1 1 read-write DIVBYZERO When DIV_0_TRP (see Configuration Control Register on page 8-26) is enabled and an SDIV or UDIV instruction is used with a divisor of 0, this fault occurs The instruction is executed and the return PC points to it. If DIV_0_TRP is not set, then the divide returns a quotient of 0. 25 1 read-write IACCVIOL Instruction access violation flag. Attempting to fetch an instruction from a location that does not permit execution sets the IACCVIOL flag. This occurs on any access to an XN region, even when the MPU is disabled or not present. The return PC points to the faulting instruction. The MMAR is not written. 0 1 read-write IBUSERR Instruction bus error flag. The IBUSERR flag is set by a prefetch error. The fault stops on the instruction, so if the error occurs under a branch shadow, no fault occurs. The BFAR is not written. 8 1 read-write IMPRECISERR Imprecise data bus error. It is a BusFault, but the Return PC is not related to the causing instruction. This is not a synchronous fault. So, if detected when the priority of the current activation is higher than the Bus Fault, it only pends. Bus fault activates when returning to a lower priority activation. If a precise fault occurs before returning to a lower priority exception, the handler detects both IMPRECISERR set and one of the precise fault status bits set at the same time. The BFAR is not written. 10 1 read-write INVPC Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid context, invalid value. The return PC points to the instruction that tried to set the PC. 18 1 read-write INVSTATE Invalid combination of EPSR and instruction, for reasons other than UNDEFINED instruction. Return PC points to faulting instruction, with the invalid state. 17 1 read-write LSPERR Indicates if bus fault occurred during FP lazy state preservation. 13 1 read-write MLSPERR Indicates if MemManage fault occurred during FP lazy state preservation. 5 1 read-write MMARVALID Memory Manage Address Register (MMAR) address valid flag. A later-arriving fault, such as a bus fault, can clear a memory manage fault.. If a MemManage fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems on return to a stacked active MemManage handler whose MMAR value has been overwritten. 7 1 read-write MSTKERR Stacking from exception has caused one or more access violations. The SP is still adjusted and the values in the context area on the stack might be incorrect. The MMAR is not written. 4 1 read-write MUNSTKERR Unstack from exception return has caused one or more access violations. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. The MMAR is not written. 3 1 read-write NOCP Attempt to use a coprocessor instruction. The processor does not support coprocessor instructions. 19 1 read-write PRECISERR Precise data bus error return. 9 1 read-write STKERR Stacking from exception has caused one or more bus faults. The SP is still adjusted and the values in the context area on the stack might be incorrect. The BFAR is not written. 12 1 read-write UNALIGNED When UNALIGN_TRP is enabled (see Configuration Control Register on page 8-26), and there is an attempt to make an unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD instructions always fault irrespective of the setting of UNALIGN_TRP. 24 1 read-write UNDEFINSTR The UNDEFINSTR flag is set when the processor attempts to execute an undefined instruction. This is an instruction that the processor cannot decode. The return PC points to the undefined instruction. 16 1 read-write UNSTKERR Unstack from exception return has caused one or more bus faults. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. The BFAR is not written. 11 1 read-write CPACR CPACR Coprocessor Access Control Register 0xD88 32 read-write n 0x0 0x0 CP10 Access privileges for coprocessor 10. The possible values of each field are: 0b00 = Access denied. Any attempted access generates a NOCP UsageFault. 0b01 = Privileged access only. An unprivileged access generates a NOCP UsageFault. 0b10 = Reserved. 0b11 = Full access. Used in conjunction with the control for CP11, this controls access to the Floating Point Coprocessor. 20 2 read-write CP11 Access privileges for coprocessor 11. The possible values of each field are: 0b00 = Access denied. Any attempted access generates a NOCP UsageFault. 0b01 = Privileged access only. An unprivileged access generates a NOCP UsageFault. 0b10 = Reserved. 0b11 = Full access. Used in conjunction with the control for CP10, this controls access to the Floating Point Coprocessor. 22 2 read-write CPUID CPUID CPUID Base Register 0xD00 32 read-only n 0x410FC241 0x0 CONSTANT Reads as 0xC 16 4 read-only IMPLEMENTER Implementor code. 24 8 read-only PARTNO Number of processor within family. 4 12 read-only REVISION Implementation defined revision number. 0 4 read-only VARIANT Implementation defined variant number. 20 4 read-only DCRDR DCRDR Debug Core Register Data Register 0xDF8 32 read-write n 0x0 0x0 DCRSR DCRSR Deubg Core Register Selector Register 0xDF4 32 write-only n 0x0 0x0 REGSEL Register select 0 5 write-only en_0b00000 R0 0 en_0b00001 R1 1 en_0b01010 R10 10 en_0b01011 R11 11 en_0b01100 R12 12 en_0b01101 Current SP 13 en_0b01110 LR 14 en_0b01111 DebugReturnAddress 15 en_0b10000 xPSR/flags, execution state information, and exception number 16 en_0b10001 MSP (Main SP) 17 en_0b10010 PSP (Process SP) 18 en_0b00010 R2 2 en_0b10100 CONTROL bits [31:24], FAULTMASK bits [23:16], BASEPRI bits [15:8], PRIMASK bits [7:0] 20 en_0b00011 R3 3 en_0b00100 R4 4 en_0b00101 R5 5 en_0b00110 R6 6 en_0b00111 R7 7 en_0b01000 R8 8 en_0b01001 R9 9 REGWNR Write = 1, Read = 0 16 1 write-only DEMCR DEMCR Debug Exception and Monitor Control Register 0xDFC 32 read-write n 0x0 0x0 MON_EN Enable the debug monitor. When enabled, the System handler priority register controls its priority level. If disabled, then all debug events go to Hard fault. C_DEBUGEN in the Debug Halting Control and Statue register overrides this bit. Vector catching is semi-synchronous. When a matching event is seen, a Halt is requested. Because the processor can only halt on an instruction boundary, it must wait until the next instruction boundary. As a result, it stops on the first instruction of the exception handler. However, two special cases exist when a vector catch has triggered: 1. If a fault is taken during vectoring, vector read or stack push error, the halt occurs on the corresponding fault handler, for the vector error or stack push. 2. If a late arriving interrupt comes in during vectoring, it is not taken. That is, an implementation that supports the late arrival optimization must suppress it in this case. 16 1 read-write MON_PEND Pend the monitor to activate when priority permits. This can wake up the monitor through the AHB-AP port. It is the equivalent to C_HALT for Monitor debug. This register does not reset on a system reset. It is only reset by a POR reset. Software in the reset handler or later, or by the DAP must enable the debug monitor. 17 1 read-write MON_REQ This enables the monitor to identify how it wakes up. This bit clears on a Core Reset. 19 1 read-write en_0b0 woken up by debug exception. 0 en_0b1 woken up by MON_PEND 1 MON_STEP When MON_EN = 1, this steps the core. When MON_EN = 0, this bit is ignored. This is the equivalent to C_STEP. Interrupts are only stepped according to the priority of the monitor and settings of PRIMASK, FAULTMASK, or BASEPRI. 18 1 read-write TRCENA This bit must be set to 1 to enable use of the trace and debug blocks: Data Watchpoint and Trace (DWT), Instrumentation Trace Macrocell (ITM), Embedded Trace Macrocell (ETM), Trace Port Interface Unit (TPIU). This enables control of power usage unless tracing is required. The application can enable this, for ITM use, or use by a debugger. Note that if no debug or trace components are present in the implementation then it is not possible to set TRCENA. 24 1 read-write VC_BUSERR Debug Trap on normal Bus error. 8 1 read-write VC_CHKERR Debug trap on Usage Fault enabled checking errors. 6 1 read-write VC_CORERESET Reset Vector Catch. Halt running system if Core reset occurs. 0 1 read-write VC_HARDERR Debug trap on Hard Fault. 10 1 read-write VC_INTERR Debug Trap on interrupt/exception service errors. These are a subset of other faults and catches before BUSERR or HARDERR. 9 1 read-write VC_MMERR Debug trap on Memory Management faults. 4 1 read-write VC_NOCPERR Debug trap on Usage Fault access to Coprocessor that is not present or marked as not present in CAR register. 5 1 read-write VC_STATERR Debug trap on Usage Fault state errors. 7 1 read-write DFR0 DFR0 Debug Feature register0 0xD48 32 read-only n 0x100000 0x0 MICROCONTROLLER_DEBUG_MODEL Microcontroller Debug Model - memory mapped 20 4 read-only en_0b0000 not supported 0 en_0b0001 Microcontroller debug v1 (ITMv1, DWTv1, optional ETM) 1 DFSR DFSR Debug Fault Status Register 0xD30 32 read-write n 0x0 0x0 BKPT BKPT flag. The BKPT flag is set by a BKPT instruction in flash patch code, and also by normal code. Return PC points to breakpoint containing instruction. 1 1 read-write en_0b0 no BKPT instruction execution 0 en_0b1 BKPT instruction execution 1 DWTTRAP Data Watchpoint and Trace (DWT) flag. The processor stops at the current instruction or at the next instruction. 2 1 read-write en_0b0 no DWT match 0 en_0b1 DWT match 1 EXTERNAL External debug request flag. The processor stops on next instruction boundary. 4 1 read-write en_0b0 EDBGRQ signal not asserted 0 en_0b1 EDBGRQ signal asserted 1 HALTED Halt request flag. The processor is halted on the next instruction. 0 1 read-write en_0b0 no halt request 0 en_0b1 halt requested by NVIC, including step 1 VCATCH Vector catch flag. When the VCATCH flag is set, a flag in one of the local fault status registers is also set to indicate the type of fault. 3 1 read-write en_0b0 no vector catch occurred 0 en_0b1 vector catch occurred 1 DHCSR DHCSR Debug Halting Control and Status Register 0xDF0 32 read-write n 0x0 0xFFFEFFFF C_DEBUGEN Enables debug. This can only be written by AHB-AP and not by the core. It is ignored when written by the core, which cannot set or clear it. The core must write a 1 to it when writing C_HALT to halt itself. 0 1 read-write C_HALT Halts the core. This bit is set automatically when the core Halts. For example Breakpoint. This bit clears on core reset. This bit can only be written if C_DEBUGEN is 1, otherwise it is ignored. When setting this bit to 1, C_DEBUGEN must also be written to 1 in the same value (value[1:0] is 2'b11). The core can halt itself, but only if C_DEBUGEN is already 1 and only if it writes with b11). 1 1 read-write C_MASKINTS Mask interrupts when stepping or running in halted debug. Does not affect NMI, which is not maskable. Must only be modified when the processor is halted (S_HALT == 1). Also does not affect fault exceptions and SVC caused by execution of the instructions. CMASKINTS must be set or cleared before halt is released. This means that the writes to set or clear C_MASKINTS and to set or clear C_HALT must be separate. 3 1 read-write C_SNAPSTALL If the core is stalled on a load/store operation the stall ceases and the instruction is forced to complete. This enables Halting debug to gain control of the core. It can only be set if: C_DEBUGEN = 1 and C_HALT = 1. The core reads S_RETIRE_ST as 0. This indicates that no instruction has advanced. This prevents misuse. The bus state is Unpredictable when this is used. S_RETIRE can detect core stalls on load/store operations. 5 1 read-write C_STEP Steps the core in halted debug. When C_DEBUGEN = 0, this bit has no effect. Must only be modified when the processor is halted (S_HALT == 1). 2 1 read-write S_HALT The core is in debug state when S_HALT is set. 17 1 read-only S_LOCKUP Reads as one if the core is running (not halted) and a lockup condition is present. 19 1 read-only S_REGRDY Register Read/Write on the Debug Core Register Selector register is available. Last transfer is complete. 16 1 read-only S_RESET_ST Indicates that the core has been reset, or is now being reset, since the last time this bit was read. This a sticky bit that clears on read. So, reading twice and getting 1 then 0 means it was reset in the past. Reading twice and getting 1 both times means that it is being reset now (held in reset still). 25 1 read-only S_RETIRE_ST Indicates that an instruction has completed since last read. This is a sticky bit that clears on read. This determines if the core is stalled on a load/store or fetch. 24 1 read-only S_SLEEP Indicates that the core is sleeping (WFI, WFE, or SLEEP-ON-EXIT). Must use C_HALT to gain control or wait for interrupt to wake-up. 18 1 read-only FPCAR FPCAR Floating-Point Context Address Register 0xF38 32 read-write n 0x0 0x0 ADDRESS Holds the (double-word-aligned) location of the unpopulated floating-point register space allocated on an exception stack frame. 2 29 read-write FPCCR FPCCR Floating Point Context Control Register 0xF34 32 read-write n 0xC0000000 0x0 ASPEN Automatic State Preservation ENable. When this bit is set is will cause bit [2] of the Special CONTROL register to be set (FPCA) on execution of a floating point instruction which results in the floating point state automatically being preserved on exception entry. 31 1 read-write BFRDY Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending. 6 1 read-write HFRDY Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending. 4 1 read-write LSPACT Indicates whether Lazy preservation of the FP state is active. 0 1 read-write LSPEN Lazy State Preservation ENable. When the processor performs a context save, space on the stack is reserved for the floating point state but it is not stacked until the new context performs a floating point operation. 30 1 read-write MMRDY Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending. 5 1 read-write MONRDY Indicates whether the the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending. 8 1 read-write THREAD Indicates the processor mode was Thread when it allocated the FP stack frame. 3 1 read-write USER Indicates the privilege level of the software executing was User (Unpriviledged) when the processor allocated the FP stack frame. 1 1 read-write FPDSCR FPDSCR Floating Point Default Status Control Register 0xF3C 32 read-write n 0x0 0x0 AHP Default value for Alternative Half Precision bit. (If this bit is set to 1 then Alternative half-precision format is selected). 26 1 read-write DN Default value for Default NaN mode bit. (If this bit is set to 1 then any operation involving one or more NaNs returns the Default NaN). 25 1 read-write FZ Default value for Flush-to-Zero mode bit. (If this bit is set to 1 then Flush-to-zero mode is enabled). 24 1 read-write RMODE Default value for Rounding Mode control field. (The encoding for this field is: 0b00 Round to Nearest (RN) mode, 0b01 Round towards Plus Infinity (RP) mode, 0b10 Round towards Minus Infinity (RM) mode, 0b11 Round towards Zero (RZ) mode. The specified rounding mode is used by almost all floating-point instructions). 22 2 read-write HFSR HFSR Hard Fault Status Register 0xD2C 32 read-write n 0x0 0x0 DEBUGEVT This bit is set if there is a fault related to debug. This is only possible when halting debug is not enabled. For monitor enabled debug, it only happens for BKPT when the current priority is higher than the monitor. When both halting and monitor debug are disabled, it only happens for debug events that are not ignored (minimally, BKPT). The Debug Fault Status Register is updated. 31 1 read-write FORCED Hard Fault activated because a Configurable Fault was received and cannot activate because of priority or because the Configurable Fault is disabled. The Hard Fault handler then has to read the other fault status registers to determine cause. 30 1 read-write VECTTBL This bit is set if there is a fault because of vector table read on exception processing (Bus Fault). This case is always a Hard Fault. The return PC points to the pre-empted instruction. 1 1 read-write IABR0 IABR0 Irq 0 to 31 Active Bit Register 0x300 32 read-only n 0x0 0x0 ACTIVE Interrupt active flags. Reading 0 implies the interrupt is not active or stacked. Reading 1 implies the interrupt is active or pre-empted and stacked. 0 32 read-only IABR1 IABR1 Irq 32 to 63 Active Bit Register 0x304 32 read-only n 0x0 0x0 ACTIVE Interrupt active flags. Reading 0 implies the interrupt is not active or stacked. Reading 1 implies the interrupt is active or pre-empted and stacked. 0 32 read-only ICER0 ICER0 Irq 0 to 31 Clear Enable Register 0x180 32 read-write n 0x0 0x0 CLRENA Writing 0 to a CLRENA bit has no effect, writing 1 to a bit disables the corresponding interrupt. Reading the bit returns its current enable state. Reset clears the CLRENA field. 0 32 read-write ICER1 ICER1 Irq 32 to 63 Clear Enable Register 0x184 32 read-write n 0x0 0x0 CLRENA Writing 0 to a CLRENA bit has no effect, writing 1 to a bit disables the corresponding interrupt. Reading the bit returns its current enable state. Reset clears the CLRENA field. 0 32 read-write ICPR0 ICPR0 Irq 0 to 31 Clear Pending Register 0x280 32 read-write n 0x0 0x0 CLRPEND Writing 0 to a CLRPEND bit has no effect, writing 1 to a bit clears the corresponding pending interrupt. Reading the bit returns its current state. 0 32 read-write ICPR1 ICPR1 Irq 32 to 63 Clear Pending Register 0x284 32 read-write n 0x0 0x0 CLRPEND Writing 0 to a CLRPEND bit has no effect, writing 1 to a bit clears the corresponding pending interrupt. Reading the bit returns its current state. 0 32 read-write ICSR ICSR Interrupt Control State Register 0xD04 32 read-write n 0x0 0x0 ISRPENDING Interrupt pending flag. Excludes NMI and faults. 22 1 read-only en_0b0 interrupt not pending 0 en_0b1 interrupt pending 1 ISRPREEMPT You must only use this at debug time. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced. 23 1 read-only en_0b0 a pending exception is not serviced. 0 en_0b1 a pending exception is serviced on exit from the debug halt state 1 NMIPENDSET Set pending NMI bit. NMIPENDSET pends and activates an NMI. Because NMI is the highest-priority interrupt, it takes effect as soon as it registers. 31 1 read-write en_0b0 do not set pending NMI 0 en_0b1 set pending NMI 1 PENDSTCLR Clear pending SysTick bit 25 1 write-only en_0b0 do not clear pending SysTick 0 en_0b1 clear pending SysTick 1 PENDSTSET Set a pending SysTick bit. 26 1 read-write en_0b0 do not set pending SysTick 0 en_0b1 set pending SysTick 1 PENDSVCLR Clear pending pendSV bit 27 1 write-only en_0b0 do not clear pending pendSV 0 en_0b1 clear pending pendSV 1 PENDSVSET Set pending pendSV bit. 28 1 read-write en_0b0 do not set pending pendSV 0 en_0b1 set pending PendSV 1 RETTOBASE This bit is 1 when the set of all active exceptions minus the IPSR_current_exception yields the empty set. 11 1 read-only VECTACTIVE Active ISR number field. Reset clears the VECTACTIVE field. 0 9 read-only VECTPENDING Pending ISR number field. VECTPENDING contains the interrupt number of the highest priority pending ISR. 12 6 read-only ICTR ICTR Interrupt Control Type Register 0x4 32 read-only n 0x0 0x0 INTLINESNUM Total number of interrupt lines in groups of 32. 0 5 read-only IPR0 IPR0 Irq 0 to 3 Priority Register 0x400 32 read-write n 0x0 0x0 PRI_0 Priority of interrupt 0 0 8 read-write PRI_1 Priority of interrupt 1 8 8 read-write PRI_2 Priority of interrupt 2 16 8 read-write PRI_3 Priority of interrupt 3 24 8 read-write IPR1 IPR1 Irq 4 to 7 Priority Register 0x404 32 read-write n 0x0 0x0 PRI_4 Priority of interrupt 4 0 8 read-write PRI_5 Priority of interrupt 5 8 8 read-write PRI_6 Priority of interrupt 6 16 8 read-write PRI_7 Priority of interrupt 7 24 8 read-write IPR10 IPR10 Irq 40 to 43 Priority Register 0x428 32 read-write n 0x0 0x0 PRI_40 Priority of interrupt 40 0 8 read-write PRI_41 Priority of interrupt 41 8 8 read-write PRI_42 Priority of interrupt 42 16 8 read-write PRI_43 Priority of interrupt 43 24 8 read-write IPR11 IPR11 Irq 44 to 47 Priority Register 0x42C 32 read-write n 0x0 0x0 PRI_44 Priority of interrupt 44 0 8 read-write PRI_45 Priority of interrupt 45 8 8 read-write PRI_46 Priority of interrupt 46 16 8 read-write PRI_47 Priority of interrupt 47 24 8 read-write IPR12 IPR12 Irq 48 to 51 Priority Register 0x430 32 read-write n 0x0 0x0 PRI_48 Priority of interrupt 48 0 8 read-write PRI_49 Priority of interrupt 49 8 8 read-write PRI_50 Priority of interrupt 50 16 8 read-write PRI_51 Priority of interrupt 51 24 8 read-write IPR13 IPR13 Irq 52 to 55 Priority Register 0x434 32 read-write n 0x0 0x0 PRI_52 Priority of interrupt 52 0 8 read-write PRI_53 Priority of interrupt 53 8 8 read-write PRI_54 Priority of interrupt 54 16 8 read-write PRI_55 Priority of interrupt 55 24 8 read-write IPR14 IPR14 Irq 56 to 59 Priority Register 0x438 32 read-write n 0x0 0x0 PRI_56 Priority of interrupt 56 0 8 read-write PRI_57 Priority of interrupt 57 8 8 read-write PRI_58 Priority of interrupt 58 16 8 read-write PRI_59 Priority of interrupt 59 24 8 read-write IPR15 IPR15 Irq 60 to 63 Priority Register 0x43C 32 read-write n 0x0 0x0 PRI_60 Priority of interrupt 60 0 8 read-write PRI_61 Priority of interrupt 61 8 8 read-write PRI_62 Priority of interrupt 62 16 8 read-write PRI_63 Priority of interrupt 63 24 8 read-write IPR2 IPR2 Irq 8 to 11 Priority Register 0x408 32 read-write n 0x0 0x0 PRI_10 Priority of interrupt 10 16 8 read-write PRI_11 Priority of interrupt 11 24 8 read-write PRI_8 Priority of interrupt 8 0 8 read-write PRI_9 Priority of interrupt 9 8 8 read-write IPR3 IPR3 Irq 12 to 15 Priority Register 0x40C 32 read-write n 0x0 0x0 PRI_12 Priority of interrupt 12 0 8 read-write PRI_13 Priority of interrupt 13 8 8 read-write PRI_14 Priority of interrupt 14 16 8 read-write PRI_15 Priority of interrupt 15 24 8 read-write IPR4 IPR4 Irq 16 to 19 Priority Register 0x410 32 read-write n 0x0 0x0 PRI_16 Priority of interrupt 16 0 8 read-write PRI_17 Priority of interrupt 17 8 8 read-write PRI_18 Priority of interrupt 18 16 8 read-write PRI_19 Priority of interrupt 19 24 8 read-write IPR5 IPR5 Irq 20 to 23 Priority Register 0x414 32 read-write n 0x0 0x0 PRI_20 Priority of interrupt 20 0 8 read-write PRI_21 Priority of interrupt 21 8 8 read-write PRI_22 Priority of interrupt 22 16 8 read-write PRI_23 Priority of interrupt 23 24 8 read-write IPR6 IPR6 Irq 24 to 27 Priority Register 0x418 32 read-write n 0x0 0x0 PRI_24 Priority of interrupt 24 0 8 read-write PRI_25 Priority of interrupt 25 8 8 read-write PRI_26 Priority of interrupt 26 16 8 read-write PRI_27 Priority of interrupt 27 24 8 read-write IPR7 IPR7 Irq 28 to 31 Priority Register 0x41C 32 read-write n 0x0 0x0 PRI_28 Priority of interrupt 28 0 8 read-write PRI_29 Priority of interrupt 29 8 8 read-write PRI_30 Priority of interrupt 30 16 8 read-write PRI_31 Priority of interrupt 31 24 8 read-write IPR8 IPR8 Irq 32 to 35 Priority Register 0x420 32 read-write n 0x0 0x0 PRI_32 Priority of interrupt 32 0 8 read-write PRI_33 Priority of interrupt 33 8 8 read-write PRI_34 Priority of interrupt 34 16 8 read-write PRI_35 Priority of interrupt 35 24 8 read-write IPR9 IPR9 Irq 36 to 39 Priority Register 0x424 32 read-write n 0x0 0x0 PRI_36 Priority of interrupt 36 0 8 read-write PRI_37 Priority of interrupt 37 8 8 read-write PRI_38 Priority of interrupt 38 16 8 read-write PRI_39 Priority of interrupt 39 24 8 read-write ISAR0 ISAR0 ISA Feature register0 0xD60 32 read-only n 0x1141110 0x0 BITCOUNT_INSTRS BitCount instructions 4 4 read-only en_0b0000 no bit-counting instructions present 0 en_0b0001 adds CLZ 1 BITFIELD_INSTRS BitField instructions 8 4 read-only en_0b0000 no bitfield instructions present 0 en_0b0001 adds BFC, BFI, SBFX, UBFX 1 CMPBRANCH_INSTRS CmpBranch instructions 12 4 read-only en_0b0000 no combined compare-and-branch instructions present 0 en_0b0001 adds CB{N}Z 1 COPROC_INSTRS Coprocessor instructions 16 4 read-only en_0b0000 no coprocessor support, other than for separately attributed architectures such as CP15 or VFP 0 en_0b0001 adds generic CDP, LDC, MCR, MRC, STC 1 en_0b0010 adds generic CDP2, LDC2, MCR2, MRC2, STC2 2 en_0b0011 adds generic MCRR, MRRC 3 en_0b0100 adds generic MCRR2, MRRC2 4 DEBUG_INSTRS Debug instructions 20 4 read-only en_0b0000 no debug instructions present 0 en_0b0001 adds BKPT 1 DIVIDE_INSTRS Divide instructions 24 4 read-only en_0b0000 no divide instructions present 0 en_0b0001 adds SDIV, UDIV (v1 quotient only result) 1 ISAR1 ISAR1 ISA Feature register1 0xD64 32 read-only n 0x2112000 0x0 EXTEND_INSRS Extend instructions. Note that the shift options on these instructions are also controlled by the WithShifts_instrs attribute. 12 4 read-only en_0b0000 no scalar (i.e. non-SIMD) sign/zero-extend instructions present 0 en_0b0001 adds SXTB, SXTH, UXTB, UXTH 1 en_0b0010 N/A 2 IFTHEN_INSTRS IfThen instructions 16 4 read-only en_0b0000 IT instructions not present 0 en_0b0001 adds IT instructions (and IT bits in PSRs) 1 IMMEDIATE_INSTRS Immediate instructions 20 4 read-only en_0b0000 no special immediate-generating instructions present 0 en_0b0001 adds ADDW, MOVW, MOVT, SUBW 1 INTERWORK_INSTRS Interwork instructions 24 4 read-only en_0b0000 no interworking instructions supported 0 en_0b0001 adds BX (and T bit in PSRs) 1 en_0b0010 adds BLX, and PC loads have BX-like behavior 2 en_0b0011 N/A 3 ISAR2 ISAR2 ISA Feature register2 0xD68 32 read-only n 0x21232231 0x0 LOADSTORE_INSTRS LoadStore instructions 0 4 read-only en_0b0000 no additional normal load/store instructions present 0 en_0b0001 adds LDRD/STRD 1 MEMHINT_INSTRS MemoryHint instructions 4 4 read-only en_0b0000 no memory hint instructions presen 0 en_0b0001 adds PLD 1 en_0b0010 adds PLD (ie a repeat on value 1) 2 en_0b0011 adds PLI 3 MULTIACCESSINT_INSTRS Multi-Access interruptible instructions 8 4 read-only en_0b0000 the (LDM/STM) instructions are non-interruptible 0 en_0b0001 the (LDM/STM) instructions are restartable 1 en_0b0010 the (LDM/STM) instructions are continuable 2 MULTS_INSTRS Multiply instructions (advanced, signed) 16 4 read-only en_0b0000 no signed multiply instructions present 0 en_0b0001 adds SMULL, SMLAL 1 en_0b0010 N/A 2 en_0b0011 N/A 3 MULTU_INSTRS Multiply instructions (advanced, unsigned) 20 4 read-only en_0b0000 no unsigned multiply instructions present 0 en_0b0001 adds UMULL, UMLAL 1 en_0b0010 N/A 2 MULT_INSTRS Multiply instructions 12 4 read-only en_0b0000 only MUL present 0 en_0b0001 adds MLA 1 en_0b0010 adds MLS 2 REVERSAL_INSTRS Reversal instructions 28 4 read-only en_0b0000 no reversal instructions present 0 en_0b0001 adds REV, REV16, REVSH 1 en_0b0010 adds RBIT 2 ISAR3 ISAR3 ISA Feature register3 0xD6C 32 read-only n 0x1111131 0x0 SATRUATE_INSTRS Saturate instructions 0 4 read-only en_0b0000 no non-SIMD saturate instructions present 0 en_0b0001 N/A 1 SIMD_INSTRS SIMD instructions 4 4 read-only en_0b0000 no SIMD instructions present 0 en_0b0001 adds SSAT, USAT (and the Q flag in the PSRs) 1 en_0b0011 N/A 3 SVC_INSTRS SVC instructions 8 4 read-only en_0b0000 no SVC (SWI) instructions present 0 en_0b0001 adds SVC (SWI) 1 SYNCPRIM_INSTRS SyncPrim instructions. Note there are no LDREXD or STREXD in ARMv7-M. This attribute is used in conjunction with the SyncPrim_instrs_frac attribute in ID_ISAR4[23:20]. 12 4 read-only en_0b0000 no synchronization primitives present 0 en_0b0001 adds LDREX, STREX 1 en_0b0010 adds LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, CLREX(N/A) 2 TABBRANCH_INSTRS TableBranch instructions 16 4 read-only en_0b0000 no table-branch instructions present 0 en_0b0001 adds TBB, TBH 1 THUMBCOPY_INSTRS ThumbCopy instructions 20 4 read-only en_0b0000 Thumb MOV(register) instruction does not allow low reg -> low reg 0 en_0b0001 adds Thumb MOV(register) low reg -> low reg and the CPY alias 1 TRUENOP_INSTRS TrueNOP instructions 24 4 read-only en_0b0000 true NOP instructions not present - that is, NOP instructions with no register dependencies 0 en_0b0001 adds "true NOP", and the capability of additional "NOP compatible hints" 1 ISAR4 ISAR4 ISA Feature register4 0xD70 32 read-only n 0x1310102 0x0 BARRIER_INSTRS Barrier instructions 16 4 read-only en_0b0000 no barrier instructions supported 0 en_0b0001 adds DMB, DSB, ISB barrier instructions 1 PSR_M_INSTRS PSR_M_instrs 24 4 read-only en_0b0000 instructions not present 0 en_0b0001 adds CPS, MRS, and MSR instructions (M-profile forms) 1 SYNCPRIM_INSTRS_FRAC SyncPrim_instrs_frac 20 4 read-only en_0b0000 no additional support 0 en_0b0011 adds CLREX, LDREXB, STREXB, LDREXH, STREXH 3 UNPRIV_INSTRS Unprivileged instructions 0 4 read-only en_0b0000 no "T variant" instructions exist 0 en_0b0001 adds LDRBT, LDRT, STRBT, STRT 1 en_0b0010 adds LDRHT, LDRSBT, LDRSHT, STRHT 2 WITHSHIFTS_INSTRS WithShift instructions. Note that all additions only apply in cases where the encoding supports them - e.g. there is no difference between levels 3 and 4 in the Thumb-2 instruction set. Also note that MOV instructions with shift options should instead be treated as ASR, LSL, LSR, ROR or RRX instructions. 4 4 read-only en_0b0000 non-zero shifts only support MOV and shift instructions (see notes) 0 en_0b0001 shifts of loads/stores over the range LSL 0-3 1 en_0b0010 adds other constant shift options. 3 en_0b0100 adds register-controlled shift options. 4 WRITEBACK_INSTRS Writeback instructions 8 4 read-only en_0b0000 only non-writeback addressing modes present, except that LDMIA/STMDB/PUSH/POP instructions support writeback addressing. 0 en_0b0001 adds all currently-defined writeback addressing modes (ARMv7, Thumb-2) 1 ISER0 ISER0 Irq 0 to 31 Set Enable Register 0x100 32 read-write n 0x0 0x0 SETENA Writing 0 to a SETENA bit has no effect, writing 1 to a bit enables the corresponding interrupt. Reading the bit returns its current enable state. Reset clears the SETENA fields. 0 32 read-write ISER1 ISER1 Irq 32 to 63 Set Enable Register 0x104 32 read-write n 0x0 0x0 SETENA Writing 0 to a SETENA bit has no effect, writing 1 to a bit enables the corresponding interrupt. Reading the bit returns its current enable state. Reset clears the SETENA fields. 0 32 read-write ISPR0 ISPR0 Irq 0 to 31 Set Pending Register 0x200 32 read-write n 0x0 0x0 SETPEND Writing 0 to a SETPEND bit has no effect, writing 1 to a bit pends the corresponding interrupt. Reading the bit returns its current state. 0 32 read-write ISPR1 ISPR1 Irq 32 to 63 Set Pending Register 0x204 32 read-write n 0x0 0x0 SETPEND Writing 0 to a SETPEND bit has no effect, writing 1 to a bit pends the corresponding interrupt. Reading the bit returns its current state. 0 32 read-write MMFAR MMFAR Mem Manage Fault Address Register 0xD34 32 read-write n 0x0 0x0 ADDRESS Mem Manage fault address field. ADDRESS is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the actual address that faulted. Because an access can be split into multiple parts, each aligned, this address can be any offset in the range of the requested size. Flags in the Memory Manage Fault Status Register indicate the cause of the fault 0 32 read-write MMFR0 MMFR0 Memory Model Feature register0 0xD50 32 read-only n 0x100030 0x0 AUXILIARY_REGISTER_SUPPORT Auxiliary register support 20 4 read-only en_0b0000 not supported 0 en_0b0001 Auxiliary control register 1 CACHE_COHERENCE_SUPPORT Cache coherence support 8 4 read-only en_0b0000 no shared support 0 en_0b0001 partial-inner-shared coherency (coherency amongst some - but not all - of the entities within an inner-coherent domain) 1 en_0b0010 full-inner-shared coherency (coherency amongst all of the entities within an inner-coherent domain) 2 en_0b0011 full coherency (coherency amongst all of the entities) 3 OUTER_NON_SHARABLE_SUPPORT Outer non-sharable support 12 4 read-only en_0b0000 Outer non-sharable not supported 0 en_0b0001 Outer sharable supported 1 PMSA_SUPPORT PMSA support 4 4 read-only en_0b0000 not supported 0 en_0b0001 IMPLEMENTATION DEFINED (N/A) 1 en_0b0010 PMSA base (features as defined for ARMv6) (N/A) 2 en_0b0011 PMSAv7 (base plus subregion support) 3 MMFR1 MMFR1 Memory Model Feature register1 0xD54 32 read-only n 0x0 0x0 MMFR2 MMFR2 Memory Model Feature register2 0xD58 32 read-only n 0x0 0x0 WAIT_FOR_INTERRUPT_STALLING wait for interrupt stalling 24 4 read-only en_0b0000 not supported 0 en_0b0001 wait for interrupt supported 1 MMFR3 MMFR3 Memory Model Feature register3 0xD5C 32 read-only n 0x0 0x0 MPU_CTRL CTRL MPU Control Register 0xD94 32 read-write n 0x0 0x0 ENABLE MPU enable bit. Reset clears the ENABLE bit. 0 1 read-write en_0b0 disable MPU 0 en_0b1 enable MPU 1 HFNMIENA This bit enables the MPU when in Hard Fault, NMI, and FAULTMASK escalated handlers. If this bit = 1 and the ENABLE bit = 1, the MPU is enabled when in these handlers. If this bit = 0, the MPU is disabled when in these handlers, regardless of the value of ENABLE. If this bit =1 and ENABLE = 0, behavior is Unpredictable. Reset clears the HFNMIENA bit. 1 1 read-write PRIVDEFENA This bit enables the default memory map for privileged access, as a background region, when the MPU is enabled. The background region acts as if it was region number 1 before any settable regions. Any region that is set up overlays this default map, and overrides it. If this bit = 0, the default memory map is disabled, and memory not covered by a region faults. This applies to memory type, Execute Never (XN), cache and shareable rules. However, this only applies to privileged mode (fetch and data access). User mode code faults unless a region has been set up for its code and data. When the MPU is disabled, the default map acts on both privileged and user mode code. XN and SO rules always apply to the System partition whether this enable is set or not. If the MPU is disabled, this bit is ignored. Reset clears the PRIVDEFENA bit. 2 1 read-write MPU_RASR RASR MPU Region Attribute and Size Register 0xDA0 32 read-write n 0x0 0x0 AP Data access permission field 24 3 read-write en_0b000 Priviliged permissions: No access. User permissions: No access. 0 en_0b001 Priviliged permissions: Read-write. User permissions: No access. 1 en_0b010 Priviliged permissions: Read-write. User permissions: Read-only. 2 en_0b011 Priviliged permissions: Read-write. User permissions: Read-write. 3 en_0b101 Priviliged permissions: Read-only. User permissions: No access. 5 en_0b110 Priviliged permissions: Read-only. User permissions: Read-only. 6 en_0b111 Priviliged permissions: Read-only. User permissions: Read-only. 7 B Bufferable bit 16 1 read-write en_0b0 not bufferable 0 en_0b1 bufferable 1 C Cacheable bit 17 1 read-write en_0b0 not cacheable 0 en_0b1 cacheable 1 ENABLE Region enable bit. 0 1 read-write S Shareable bit 18 1 read-write en_0b0 not shareable 0 en_0b1 shareable 1 SIZE MPU Protection Region Size Field. 1 5 read-write en_0b01010 2KB 10 en_0b01011 4KB 11 en_0b01100 8KB 12 en_0b01101 16KB 13 en_0b01110 32KB 14 en_0b01111 64KB 15 en_0b10000 128KB 16 en_0b10001 256KB 17 en_0b10010 512KB 18 en_0b10011 1MB 19 en_0b10100 2MB 20 en_0b10101 4MB 21 en_0b10110 8MB 22 en_0b10111 16MB 23 en_0b11000 32MB 24 en_0b11001 64MB 25 en_0b11010 128MB 26 en_0b11011 256MB 27 en_0b11100 512MB 28 en_0b11101 1GB 29 en_0b11110 2GB 30 en_0b11111 4GB 31 en_0b00100 32B 4 en_0b00101 64B 5 en_0b00110 128B 6 en_0b00111 256B 7 en_0b01000 512B 8 en_0b01001 1KB 9 SRD Sub-Region Disable (SRD) field. Setting an SRD bit disables the corresponding sub-region. Regions are split into eight equal-sized sub-regions. Sub-regions are not supported for region sizes of 128 bytes and less. 8 8 read-write TEX Type extension field 19 3 read-write XN Instruction access disable bit 28 1 read-write en_0b0 enable instruction fetches 0 en_0b1 disable instruction fetches 1 MPU_RASR_A1 RASR_A1 MPU Alias 1 Region Attribute and Size register 0xDA8 32 read-write n 0x0 0x0 MPU_RASR_A2 RASR_A2 MPU Alias 2 Region Attribute and Size register 0xDB0 32 read-write n 0x0 0x0 MPU_RASR_A3 RASR_A3 MPU Alias 3 Region Attribute and Size register 0xDB8 32 read-write n 0x0 0x0 MPU_RBAR RBAR MPU Region Base Address Register 0xD9C 32 read-write n 0x0 0x0 ADDR Region base address field. The position of the LSB depends on the region size, so that the base address is aligned according to an even multiple of size. The power of 2 size specified by the SZENABLE field of the MPU Region Attribute and Size Register defines how many bits of base address are used. 5 27 read-write REGION MPU region override field. 0 4 read-write VALID MPU Region Number valid bit. 4 1 read-write en_0b0 MPU Region Number Register remains unchanged and is interpreted. 0 en_0b1 MPU Region Number Register is overwritten by bits 3:0 (the REGION value). 1 MPU_RBAR_A1 RBAR_A1 MPU Alias 1 Region Base Address register 0xDA4 32 read-write n 0x0 0x0 MPU_RBAR_A2 RBAR_A2 MPU Alias 2 Region Base Address register 0xDAC 32 read-write n 0x0 0x0 MPU_RBAR_A3 RBAR_A3 MPU Alias 3 Region Base Address register 0xDB4 32 read-write n 0x0 0x0 MPU_RNR RNR MPU Region Number Register 0xD98 32 read-write n 0x0 0x0 REGION Region select field. Selects the region to operate on when using the Region Attribute and Size Register and the Region Base Address Register. It must be written first except when the address VALID + REGION fields are written, which overwrites this. 0 8 read-write MPU_TYPE TYPE MPU Type Register 0xD90 32 read-only n 0x800 0x0 DREGION Number of supported MPU regions field. DREGION contains 0x08 if the implementation contains an MPU indicating eight MPU regions, otherwise it contains 0x00. 8 8 read-only IREGION Because the processor core uses only a unified MPU, IREGION always contains 0x00. 16 8 read-only SEPARATE Because the processor core uses only a unified MPU, SEPARATE is always 0. 0 1 read-only MVFR0 MVFR0 Media and FP Feature Register 0 (MVFR0) 0xF40 32 read-only n 0x10110021 0x0 A_SIMD_REGISTERS Indicates the size of the FP register bank. The value of this field is: 0b0001 - supported, 16 x 64-bit registers. 0 4 read-only DIVIDE Indicates the hardware support for FP divide operations. The value of this field is: 0b0001 - supported. 16 4 read-only DOUBLE_PRECISION Indicates the hardware support for FP double-precision operations. The value of this field is: 0b0000 - not supported in ARMv7-M. 8 4 read-only FP_EXCEPTION_TRAPPING Indicates whether the FP hardware implementation supports exception trapping. The value of this field is: 0b0000 - not supported in ARMv7-M. 12 4 read-only FP_ROUNDING_MODES Indicates the rounding modes supported by the FP floating-point hardware. The value of this field is: 0b0001 - all rounding modes supported. 28 4 read-only SHORT_VECTORS Indicates the hardware support for FP short vectors. The value of this field is: 0b0000 - not supported in ARMv7-M. 24 4 read-only SINGLE_PRECISION Indicates the hardware support for FP single-precision operations. The value of this field is: 0b0010 - supported. 4 4 read-only SQUARE_ROOT Indicates the hardware support for FP square root operations. The value of this field is: 0b0001 - supported. 20 4 read-only MVFR1 MVFR1 Media and FP Feature Register 1 (MVFR1) 0xF44 32 read-only n 0x11000011 0x0 D_NAN_MODE Indicates whether the FP hardware implementation supports only the Default NaN mode. The value of this field is: 0b0001 - hardware supports propagation of NaN values. 4 4 read-only FP_FUSED_MAC Indicates whether the FP supports fused multiply accumulate operations. The value of this field is: 0b0001 - supported. 28 4 read-only FP_HPFP Indicates whether the FP supports half-precision floating-point conversion operations. The value of this field is: 0b0001 - supported. 24 4 read-only FTZ_MODE Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation. The value of this field is: 0b0001 - hardware supports full denormalized number arithmetic. 0 4 read-only PFR0 PFR0 Processor Feature register0 0xD40 32 read-only n 0x30 0x0 STATE0 State0 (T-bit == 0) 0 4 read-only en_0b0000 no ARM encoding 0 en_0b0001 N/A 1 STATE1 State1 (T-bit == 1) 4 4 read-only en_0b0000 N/A 0 en_0b0001 N/A 1 en_0b0010 Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL but no other 32-bit basic instructions (Note non-basic 32-bit instructions can be added using the appropriate instruction attribute, but other 32-bit basic instructions cannot.) 2 en_0b0011 Thumb-2 encoding with all Thumb-2 basic instructions 3 PFR1 PFR1 Processor Feature register1 0xD44 32 read-only n 0x200 0x0 MICROCONTROLLER_PROGRAMMERS_MODEL Microcontroller programmer's model 8 4 read-only en_0b0000 not supported 0 en_0b0010 two-stack support 2 SCR SCR System Control Register 0xD10 32 read-write n 0x0 0x0 SEVONPEND When enabled, this causes WFE to wake up when an interrupt moves from inactive to pended. Otherwise, WFE only wakes up from an event signal, external and SEV instruction generated. The event input, RXEV, is registered even when not waiting for an event, and so effects the next WFE. 4 1 read-write SLEEPDEEP Sleep deep bit. 2 1 read-write en_0b0 not OK to turn off system clock 0 en_0b1 indicates to the system that Cortex-M4 clock can be stopped. Setting this bit causes the SLEEPDEEP port to be asserted when the processor can be stopped. 1 SLEEPONEXIT Sleep on exit when returning from Handler mode to Thread mode. Enables interrupt driven applications to avoid returning to empty main application. 1 1 read-write en_0b0 do not sleep when returning to thread mode 0 en_0b1 sleep on ISR exit 1 SHCSR SHCSR System Handler Control and State Register 0xD24 32 read-write n 0x0 0x0 BUSFAULTACT BusFault active flag. 1 1 read-only en_0b0 not active 0 en_0b1 active 1 BUSFAULTENA Bus fault system handler enable 17 1 read-write en_0b0 disabled 0 en_0b1 enabled 1 BUSFAULTPENDED BusFault pended flag. 14 1 read-only en_0b0 not pended 0 en_0b1 pended 1 MEMFAULTACT MemManage active flag. 0 1 read-only en_0b0 not active 0 en_0b1 active 1 MEMFAULTENA MemManage fault system handler enable 16 1 read-write en_0b0 disabled 0 en_0b1 enabled 1 MEMFAULTPENDED MemManage pended flag. 13 1 read-only en_0b0 not pended 0 en_0b1 pended 1 MONITORACT the Monitor active flag. 8 1 read-only en_0b0 not active 0 en_0b1 active 1 PENDSVACT PendSV active flag. 10 1 read-only en_0b0 not active 0 en_0b1 active 1 SVCALLACT SVCall active flag. 7 1 read-only en_0b0 not active 0 en_0b1 active 1 SVCALLPENDED SVCall pended flag. 15 1 read-only en_0b0 not pended 0 en_0b1 pended 1 SYSTICKACT SysTick active flag. 11 1 read-only en_0b0 not active 0 en_0b1 active 1 USGFAULTACT UsageFault active flag. 3 1 read-only en_0b0 not active 0 en_0b1 active 1 USGFAULTENA Usage fault system handler enable 18 1 read-write en_0b0 disabled 0 en_0b1 enabled 1 USGFAULTPENDED usage fault pended flag. 12 1 read-only en_0b0 not pended 0 en_0b1 pended 1 SHPR1 SHPR1 System Handlers 4-7 Priority Register 0xD18 32 read-write n 0x0 0x0 PRI_4 Priority of system handler 4. 0 8 read-write PRI_5 Priority of system handler 5. 8 8 read-write PRI_6 Priority of system handler 6. 16 8 read-write PRI_7 Priority of system handler 7. 24 8 read-write SHPR2 SHPR2 System Handlers 8-11 Priority Register 0xD1C 32 read-write n 0x0 0x0 PRI_10 Priority of system handler 10. 16 8 read-write PRI_11 Priority of system handler 11. 24 8 read-write PRI_8 Priority of system handler 8. 0 8 read-write PRI_9 Priority of system handler 9. 8 8 read-write SHPR3 SHPR3 System Handlers 12-15 Priority Register 0xD20 32 read-write n 0x0 0x0 PRI_12 Priority of system handler 12. 0 8 read-write PRI_13 Priority of system handler 13. 8 8 read-write PRI_14 Priority of system handler 14. 16 8 read-write PRI_15 Priority of system handler 15. 24 8 read-write STCR STCR SysTick Calibration Value Register 0x1C 32 read-only n 0x0 0x0 NOREF Reads as one. Indicates that no separate reference clock is provided. 31 1 read-only SKEW Reads as one. The calibration value is not exactly 10ms because of clock frequency. This could affect its suitability as a software real time clock. 30 1 read-only TENMS Reads as zero. Indicates calibration value is not known. 0 24 read-only STCSR STCSR SysTick Control and Status Register 0x10 32 read-write n 0x4 0xFFFFFFFF CLKSOURCE Clock source. 2 1 read-only CLKSOURCE_enum_read read VAL_0 Not applicable 0 VAL_1 Core clock 1 COUNTFLAG Returns 1 if timer counted to 0 since last time this was read. Clears on read by application of any part of the SysTick Control and Status Register. If read by the debugger using the DAP, this bit is cleared on read-only if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, the COUNTFLAG bit is not changed by the debugger read. 16 1 read-only ENABLE Enable SysTick counter 0 1 read-write First Counter disabled 0 TICKINT 1 1 read-write VAL_0 Counting down to zero does not pend the SysTick handler. Software can use COUNTFLAG to determine if the SysTick handler has ever counted to zero. 0 VAL_1 Counting down to zero pends the SysTick handler. 1 STCVR STCVR SysTick Current Value Register 0x18 32 read-write n 0x0 0x0 CURRENT Current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. 0 24 read-write STIR STIR Software Trigger Interrupt Register 0xF00 32 write-only n 0x0 0x0 INTID Interrupt ID field. Writing a value to the INTID field is the same as manually pending an interrupt by setting the corresponding interrupt bit in an Interrupt Set Pending Register. 0 9 write-only STRVR STRVR SysTick Reload Value Register 0x14 32 read-write n 0x0 0x0 RELOAD Value to load into the SysTick Current Value Register when the counter reaches 0. 0 24 read-write VTOR VTOR Vector Table Offset Register 0xD08 32 read-write n 0x0 0x0 TBLBASE Table base is in Code (0) or RAM (1). 29 1 read-write TBLOFF Vector table base offset field. Contains the offset of the table base from the bottom of the SRAM or CODE space. 7 22 read-write TIMER32 TIMER32 TIMER32 0x4000C000 0x0 0xF0C registers n T32_INT1_IRQ T32_INT1 Interrupt 25 T32_INT2_IRQ T32_INT2 Interrupt 26 T32_INTC_IRQ T32_INTC Interrupt 27 T32BGLOAD1 BGLOAD1 Timer 1 Background Load Register 0x18 32 read-write n 0x0 0xFFFFFFFF BGLOAD Value from which the counter decrements 0 32 read-write T32BGLOAD2 BGLOAD2 Timer 2 Background Load Register 0x38 32 read-write n 0x0 0xFFFFFFFF BGLOAD Value from which the counter decrements 0 32 read-write T32CONTROL1 CONTROL1 Timer 1 Timer Control Register 0x8 32 read-write n 0x20 0xFFFFFFFF ENABLE Enable bit 7 1 read-write ENABLE_0 Timer disabled 0 ENABLE_1 Timer enabled 1 IE Interrupt enable bit 5 1 read-write IE_0 Timer interrupt disabled 0 IE_1 Timer interrupt enabled 1 MODE Mode bit 6 1 read-write MODE_0 Timer is in free-running mode 0 MODE_1 Timer is in periodic mode 1 ONESHOT Selects one-shot or wrapping counter mode 0 1 read-write ONESHOT_0 wrapping mode 0 ONESHOT_1 one-shot mode 1 PRESCALE Prescale bits 2 2 read-write PRESCALE_0 0 stages of prescale, clock is divided by 1 0 PRESCALE_1 4 stages of prescale, clock is divided by 16 1 PRESCALE_2 8 stages of prescale, clock is divided by 256 2 SIZE Selects 16 or 32 bit counter operation 1 1 read-write SIZE_0 16-bit counter 0 SIZE_1 32-bit counter 1 T32CONTROL2 CONTROL2 Timer 2 Timer Control Register 0x28 32 read-write n 0x20 0xFFFFFFFF ENABLE Enable bit 7 1 read-write ENABLE_0 Timer disabled 0 ENABLE_1 Timer enabled 1 IE Interrupt enable bit 5 1 read-write IE_0 Timer interrupt disabled 0 IE_1 Timer interrupt enabled 1 MODE Mode bit 6 1 read-write MODE_0 Timer is in free-running mode 0 MODE_1 Timer is in periodic mode 1 ONESHOT Selects one-shot or wrapping counter mode 0 1 read-write ONESHOT_0 wrapping mode 0 ONESHOT_1 one-shot mode 1 PRESCALE Prescale bits 2 2 read-write PRESCALE_0 0 stages of prescale, clock is divided by 1 0 PRESCALE_1 4 stages of prescale, clock is divided by 16 1 PRESCALE_2 8 stages of prescale, clock is divided by 256 2 SIZE Selects 16 or 32 bit counter operation 1 1 read-write SIZE_0 16-bit counter 0 SIZE_1 32-bit counter 1 T32INTCLR1 INTCLR1 Timer 1 Interrupt Clear Register 0xC 32 write-only n 0x0 0x0 INTCLR Write clears interrupt output 0 32 write-only T32INTCLR2 INTCLR2 Timer 2 Interrupt Clear Register 0x2C 32 write-only n 0x0 0x0 INTCLR Write clears the interrupt output 0 32 write-only T32LOAD1 LOAD1 Timer 1 Load Register 0x0 32 read-write n 0x0 0xFFFFFFFF LOAD The value from which the Timer 1 counter decrements 0 32 read-write T32LOAD2 LOAD2 Timer 2 Load Register 0x20 32 read-write n 0x0 0xFFFFFFFF LOAD The value from which the Timer 2 counter decrements 0 32 read-write T32MIS1 MIS1 Timer 1 Interrupt Status Register 0x14 32 read-only n 0x0 0xFFFFFFFF IFG Enabled interrupt status 0 1 read-only T32MIS2 MIS2 Timer 2 Interrupt Status Register 0x34 32 read-only n 0x0 0xFFFFFFFF IFG Enabled interrupt status 0 1 read-only T32RIS1 RIS1 Timer 1 Raw Interrupt Status Register 0x10 32 read-only n 0x0 0xFFFFFFFF RAW_IFG Raw interrupt status 0 1 read-only T32RIS2 RIS2 Timer 2 Raw Interrupt Status Register 0x30 32 read-only n 0x0 0xFFFFFFFF RAW_IFG Raw interrupt status 0 1 read-only T32VALUE1 VALUE1 Timer 1 Current Value Register 0x4 32 read-only n 0xFFFFFFFF 0xFFFFFFFF VALUE Current value 0 32 read-only T32VALUE2 VALUE2 Timer 2 Current Value Register 0x24 32 read-only n 0xFFFFFFFF 0xFFFFFFFF VALUE Current value of the decrementing counter 0 32 read-only TIMER_A0 TIMER_A0 TIMER_A0 0x40000000 0x0 0x30 registers n TA0_0_IRQ TA0_0 Interrupt 8 TA0_N_IRQ TA0_N Interrupt 9 TAxCCR0 CCR0 Timer_A Capture/Compare Register 0x12 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR1 CCR1 Timer_A Capture/Compare Register 0x14 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR2 CCR2 Timer_A Capture/Compare Register 0x16 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR3 CCR3 Timer_A Capture/Compare Register 0x18 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR4 CCR4 Timer_A Capture/Compare Register 0x1A 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR[0] CCR[%s] Timer_A Capture/Compare Register 0x24 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR[1] CCR[%s] Timer_A Capture/Compare Register 0x38 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR[2] CCR[%s] Timer_A Capture/Compare Register 0x4E 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR[3] CCR[%s] Timer_A Capture/Compare Register 0x66 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR[4] CCR[%s] Timer_A Capture/Compare Register 0x80 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCTL0 CCTL0 Timer_A Capture/Compare Control Register 0x2 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL1 CCTL1 Timer_A Capture/Compare Control Register 0x4 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL2 CCTL2 Timer_A Capture/Compare Control Register 0x6 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL3 CCTL3 Timer_A Capture/Compare Control Register 0x8 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL4 CCTL4 Timer_A Capture/Compare Control Register 0xA 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL[0] CCTL[%s] Timer_A Capture/Compare Control Register 0x4 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL[1] CCTL[%s] Timer_A Capture/Compare Control Register 0x8 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL[2] CCTL[%s] Timer_A Capture/Compare Control Register 0xE 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL[3] CCTL[%s] Timer_A Capture/Compare Control Register 0x16 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL[4] CCTL[%s] Timer_A Capture/Compare Control Register 0x20 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCTL CTL TimerAx Control Register 0x0 16 read-write n 0x0 0xFFFF ID Input divider 6 2 read-write ID_0 /1 0 ID_1 /2 1 ID_2 /4 2 ID_3 /8 3 MC Mode control 4 2 read-write MC_0 Stop mode: Timer is halted 0 MC_1 Up mode: Timer counts up to TAxCCR0 1 MC_2 Continuous mode: Timer counts up to 0FFFFh 2 MC_3 Up/down mode: Timer counts up to TAxCCR0 then down to 0000h 3 TACLR TimerA clear 2 1 read-write TAIE TimerA interrupt enable 1 1 read-write TAIE_0 Interrupt disabled 0 TAIE_1 Interrupt enabled 1 TAIFG TimerA interrupt flag 0 1 read-write TAIFG_0 No interrupt pending 0 TAIFG_1 Interrupt pending 1 TASSEL TimerA clock source select 8 2 read-write TASSEL_0 TAxCLK 0 TASSEL_1 ACLK 1 TASSEL_2 SMCLK 2 TASSEL_3 INCLK 3 TAxEX0 EX0 TimerAx Expansion 0 Register 0x20 16 read-write n 0x0 0xFFFF TAIDEX Input divider expansion 0 3 read-write TAIDEX_0 Divide by 1 0 TAIDEX_1 Divide by 2 1 TAIDEX_2 Divide by 3 2 TAIDEX_3 Divide by 4 3 TAIDEX_4 Divide by 5 4 TAIDEX_5 Divide by 6 5 TAIDEX_6 Divide by 7 6 TAIDEX_7 Divide by 8 7 TAxIV IV TimerAx Interrupt Vector Register 0x2E 16 read-only n 0x0 0xFFFF TAIV TimerA interrupt vector value 0 16 read-only TAIV_enum_read read TAIV_0 No interrupt pending 0 TAIV_10 Interrupt Source: Capture/compare 5 Interrupt Flag: TAxCCR5 CCIFG 10 TAIV_12 Interrupt Source: Capture/compare 6 Interrupt Flag: TAxCCR6 CCIFG 12 TAIV_14 Interrupt Source: Timer overflow Interrupt Flag: TAxCTL TAIFG Interrupt Priority: Lowest 14 TAIV_2 Interrupt Source: Capture/compare 1 Interrupt Flag: TAxCCR1 CCIFG Interrupt Priority: Highest 2 TAIV_4 Interrupt Source: Capture/compare 2 Interrupt Flag: TAxCCR2 CCIFG 4 TAIV_6 Interrupt Source: Capture/compare 3 Interrupt Flag: TAxCCR3 CCIFG 6 TAIV_8 Interrupt Source: Capture/compare 4 Interrupt Flag: TAxCCR4 CCIFG 8 TAxR R TimerA register 0x10 16 read-write n 0x0 0xFFFF TIMER_A1 TIMER_A1 TIMER_A1 0x40000400 0x0 0x30 registers n TA1_0_IRQ TA1_0 Interrupt 10 TA1_N_IRQ TA1_N Interrupt 11 TAxCCR0 CCR0 Timer_A Capture/Compare Register 0x12 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR1 CCR1 Timer_A Capture/Compare Register 0x14 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR2 CCR2 Timer_A Capture/Compare Register 0x16 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR3 CCR3 Timer_A Capture/Compare Register 0x18 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR4 CCR4 Timer_A Capture/Compare Register 0x1A 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR[0] CCR[%s] Timer_A Capture/Compare Register 0x24 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR[1] CCR[%s] Timer_A Capture/Compare Register 0x38 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR[2] CCR[%s] Timer_A Capture/Compare Register 0x4E 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR[3] CCR[%s] Timer_A Capture/Compare Register 0x66 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR[4] CCR[%s] Timer_A Capture/Compare Register 0x80 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCTL0 CCTL0 Timer_A Capture/Compare Control Register 0x2 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL1 CCTL1 Timer_A Capture/Compare Control Register 0x4 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL2 CCTL2 Timer_A Capture/Compare Control Register 0x6 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL3 CCTL3 Timer_A Capture/Compare Control Register 0x8 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL4 CCTL4 Timer_A Capture/Compare Control Register 0xA 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL[0] CCTL[%s] Timer_A Capture/Compare Control Register 0x4 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL[1] CCTL[%s] Timer_A Capture/Compare Control Register 0x8 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL[2] CCTL[%s] Timer_A Capture/Compare Control Register 0xE 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL[3] CCTL[%s] Timer_A Capture/Compare Control Register 0x16 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL[4] CCTL[%s] Timer_A Capture/Compare Control Register 0x20 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCTL CTL TimerAx Control Register 0x0 16 read-write n 0x0 0xFFFF ID Input divider 6 2 read-write ID_0 /1 0 ID_1 /2 1 ID_2 /4 2 ID_3 /8 3 MC Mode control 4 2 read-write MC_0 Stop mode: Timer is halted 0 MC_1 Up mode: Timer counts up to TAxCCR0 1 MC_2 Continuous mode: Timer counts up to 0FFFFh 2 MC_3 Up/down mode: Timer counts up to TAxCCR0 then down to 0000h 3 TACLR TimerA clear 2 1 read-write TAIE TimerA interrupt enable 1 1 read-write TAIE_0 Interrupt disabled 0 TAIE_1 Interrupt enabled 1 TAIFG TimerA interrupt flag 0 1 read-write TAIFG_0 No interrupt pending 0 TAIFG_1 Interrupt pending 1 TASSEL TimerA clock source select 8 2 read-write TASSEL_0 TAxCLK 0 TASSEL_1 ACLK 1 TASSEL_2 SMCLK 2 TASSEL_3 INCLK 3 TAxEX0 EX0 TimerAx Expansion 0 Register 0x20 16 read-write n 0x0 0xFFFF TAIDEX Input divider expansion 0 3 read-write TAIDEX_0 Divide by 1 0 TAIDEX_1 Divide by 2 1 TAIDEX_2 Divide by 3 2 TAIDEX_3 Divide by 4 3 TAIDEX_4 Divide by 5 4 TAIDEX_5 Divide by 6 5 TAIDEX_6 Divide by 7 6 TAIDEX_7 Divide by 8 7 TAxIV IV TimerAx Interrupt Vector Register 0x2E 16 read-only n 0x0 0xFFFF TAIV TimerA interrupt vector value 0 16 read-only TAIV_enum_read read TAIV_0 No interrupt pending 0 TAIV_10 Interrupt Source: Capture/compare 5 Interrupt Flag: TAxCCR5 CCIFG 10 TAIV_12 Interrupt Source: Capture/compare 6 Interrupt Flag: TAxCCR6 CCIFG 12 TAIV_14 Interrupt Source: Timer overflow Interrupt Flag: TAxCTL TAIFG Interrupt Priority: Lowest 14 TAIV_2 Interrupt Source: Capture/compare 1 Interrupt Flag: TAxCCR1 CCIFG Interrupt Priority: Highest 2 TAIV_4 Interrupt Source: Capture/compare 2 Interrupt Flag: TAxCCR2 CCIFG 4 TAIV_6 Interrupt Source: Capture/compare 3 Interrupt Flag: TAxCCR3 CCIFG 6 TAIV_8 Interrupt Source: Capture/compare 4 Interrupt Flag: TAxCCR4 CCIFG 8 TAxR R TimerA register 0x10 16 read-write n 0x0 0xFFFF TIMER_A2 TIMER_A2 TIMER_A2 0x40000800 0x0 0x30 registers n TA2_0_IRQ TA2_0 Interrupt 12 TA2_N_IRQ TA2_N Interrupt 13 TAxCCR0 CCR0 Timer_A Capture/Compare Register 0x12 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR1 CCR1 Timer_A Capture/Compare Register 0x14 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR2 CCR2 Timer_A Capture/Compare Register 0x16 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR3 CCR3 Timer_A Capture/Compare Register 0x18 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR4 CCR4 Timer_A Capture/Compare Register 0x1A 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR[0] CCR[%s] Timer_A Capture/Compare Register 0x24 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR[1] CCR[%s] Timer_A Capture/Compare Register 0x38 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR[2] CCR[%s] Timer_A Capture/Compare Register 0x4E 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR[3] CCR[%s] Timer_A Capture/Compare Register 0x66 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCR[4] CCR[%s] Timer_A Capture/Compare Register 0x80 16 read-write n 0x0 0xFFFF TAxR TimerA register 0 16 read-write TAxCCTL0 CCTL0 Timer_A Capture/Compare Control Register 0x2 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL1 CCTL1 Timer_A Capture/Compare Control Register 0x4 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL2 CCTL2 Timer_A Capture/Compare Control Register 0x6 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL3 CCTL3 Timer_A Capture/Compare Control Register 0x8 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL4 CCTL4 Timer_A Capture/Compare Control Register 0xA 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL[0] CCTL[%s] Timer_A Capture/Compare Control Register 0x4 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL[1] CCTL[%s] Timer_A Capture/Compare Control Register 0x8 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL[2] CCTL[%s] Timer_A Capture/Compare Control Register 0xE 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL[3] CCTL[%s] Timer_A Capture/Compare Control Register 0x16 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCCTL[4] CCTL[%s] Timer_A Capture/Compare Control Register 0x20 16 read-write n 0x0 0xFFF7 CAP Capture mode 8 1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 CCIS Capture/compare input select 12 2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 14 2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write OUT_0 Output low 0 OUT_1 Output high 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 SCCI Synchronized capture/compare input 10 1 read-write SCS Synchronize capture source 11 1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 TAxCTL CTL TimerAx Control Register 0x0 16 read-write n 0x0 0xFFFF ID Input divider 6 2 read-write ID_0 /1 0 ID_1 /2 1 ID_2 /4 2 ID_3 /8 3 MC Mode control 4 2 read-write MC_0 Stop mode: Timer is halted 0 MC_1 Up mode: Timer counts up to TAxCCR0 1 MC_2 Continuous mode: Timer counts up to 0FFFFh 2 MC_3 Up/down mode: Timer counts up to TAxCCR0 then down to 0000h 3 TACLR TimerA clear 2 1 read-write TAIE TimerA interrupt enable 1 1 read-write TAIE_0 Interrupt disabled 0 TAIE_1 Interrupt enabled 1 TAIFG TimerA interrupt flag 0 1 read-write TAIFG_0 No interrupt pending 0 TAIFG_1 Interrupt pending 1 TASSEL TimerA clock source select 8 2 read-write TASSEL_0 TAxCLK 0 TASSEL_1 ACLK 1 TASSEL_2 SMCLK 2 TASSEL_3 INCLK 3 TAxEX0 EX0 TimerAx Expansion 0 Register 0x20 16 read-write n 0x0 0xFFFF TAIDEX Input divider expansion 0 3 read-write TAIDEX_0 Divide by 1 0 TAIDEX_1 Divide by 2 1 TAIDEX_2 Divide by 3 2 TAIDEX_3 Divide by 4 3 TAIDEX_4 Divide by 5 4 TAIDEX_5 Divide by 6 5 TAIDEX_6 Divide by 7 6 TAIDEX_7 Divide by 8 7 TAxIV IV TimerAx Interrupt Vector Register 0x2E 16 read-only n 0x0 0xFFFF TAIV TimerA interrupt vector value 0 16 read-only TAIV_enum_read read TAIV_0 No interrupt pending 0 TAIV_10 Interrupt Source: Capture/compare 5 Interrupt Flag: TAxCCR5 CCIFG 10 TAIV_12 Interrupt Source: Capture/compare 6 Interrupt Flag: TAxCCR6 CCIFG 12 TAIV_14 Interrupt Source: Timer overflow Interrupt Flag: TAxCTL TAIFG Interrupt Priority: Lowest 14 TAIV_2 Interrupt Source: Capture/compare 1 Interrupt Flag: TAxCCR1 CCIFG Interrupt Priority: Highest 2 TAIV_4 Interrupt Source: Capture/compare 2 Interrupt Flag: TAxCCR2 CCIFG 4 TAIV_6 Interrupt Source: Capture/compare 3 Interrupt Flag: TAxCCR3 CCIFG 6 TAIV_8 Interrupt Source: Capture/compare 4 Interrupt Flag: TAxCCR4 CCIFG 8 TAxR R TimerA register 0x10 16 read-write n 0x0 0xFFFF TLV TLV TLV 0x201000 0x0 0x15C registers n ADC14_CAL_LEN ADC14_CAL_LEN ADC14 Calibration Length 0x90 32 read-only n 0x0 0xFFFFFFFF ADC14_CAL_TAG ADC14_CAL_TAG ADC14 Calibration Tag 0x8C 32 read-only n 0x5 0xFFFFFFFF ADC14_REF1P2V_TS30C ADC14_REF1P2V_TS30C ADC14 1.2V Reference Temp. Sensor 30C 0xDC 32 read-only n 0x0 0xFFFFFFFF ADC14_REF1P2V_TS85C ADC14_REF1P2V_TS85C ADC14 1.2V Reference Temp. Sensor 85C 0xE0 32 read-only n 0x0 0xFFFFFFFF ADC14_REF1P45V_TS30C ADC14_REF1P45V_TS30C ADC14 1.45V Reference Temp. Sensor 30C 0xE4 32 read-only n 0x0 0xFFFFFFFF ADC14_REF1P45V_TS85C ADC14_REF1P45V_TS85C ADC14 1.45V Reference Temp. Sensor 85C 0xE8 32 read-only n 0x0 0xFFFFFFFF ADC14_REF2P5V_TS30C ADC14_REF2P5V_TS30C ADC14 2.5V Reference Temp. Sensor 30C 0xEC 32 read-only n 0x0 0xFFFFFFFF ADC14_REF2P5V_TS85C ADC14_REF2P5V_TS85C ADC14 2.5V Reference Temp. Sensor 85C 0xF0 32 read-only n 0x0 0xFFFFFFFF ADC_GAIN_FACTOR ADC_GAIN_FACTOR ADC Gain Factor 0x94 32 read-only n 0x0 0xFFFFFFFF ADC_OFFSET ADC_OFFSET ADC Offset 0x98 32 read-only n 0x0 0xFFFFFFFF BCREV BCREV Boot Code Revision 0x14 32 read-only n 0x0 0xFFFFFFFF BSL_CFG_LEN BSL_CFG_LEN BSL Configuration Length 0x134 32 read-only n 0x0 0xFFFFFFFF BSL_CFG_TAG BSL_CFG_TAG BSL Configuration Tag 0x130 32 read-only n 0xF 0xFFFFFFFF BSL_PERIPHIF_SEL BSL_PERIPHIF_SEL BSL Peripheral Interface Selection 0x138 32 read-only n 0x0 0xFFFFFFFF BSL_PORTIF_CFG_I2C BSL_PORTIF_CFG_I2C BSL Port Interface Configuration for I2C 0x144 32 read-only n 0x0 0xFFFFFFFF BSL_PORTIF_CFG_SPI BSL_PORTIF_CFG_SPI BSL Port Interface Configuration for SPI 0x140 32 read-only n 0x0 0xFFFFFFFF BSL_PORTIF_CFG_UART BSL_PORTIF_CFG_UART BSL Port Interface Configuration for UART 0x13C 32 read-only n 0x0 0xFFFFFFFF CHECKSUM TLV_CHECKSUM TLV Checksum 0x0 32 read-only n 0x0 0xFFFFFFFF CS_CAL_LEN CS_CAL_LEN Clock System Calibration Length 0x48 32 read-only n 0x0 0xFFFFFFFF CS_CAL_TAG CS_CAL_TAG Clock System Calibration Tag 0x44 32 read-only n 0x3 0xFFFFFFFF DCOER_CONSTK_RSEL04 DCOER_CONSTK_RSEL04 DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 0x84 32 read-only n 0x0 0xFFFFFFFF DCOER_CONSTK_RSEL5 DCOER_CONSTK_RSEL5 DCO ER mode: DCO Constant (K) for DCORSEL 5 0x88 32 read-only n 0x0 0xFFFFFFFF DCOER_FCAL_RSEL04 DCOER_FCAL_RSEL04 DCO ER mode: Frequency calibration for DCORSEL 0 to 4 0x6C 32 read-only n 0x0 0xFFFFFFFF DCOER_FCAL_RSEL5 DCOER_FCAL_RSEL5 DCO ER mode: Frequency calibration for DCORSEL 5 0x70 32 read-only n 0x0 0xFFFFFFFF DCOIR_CONSTK_RSEL04 DCOIR_CONSTK_RSEL04 DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 0x64 32 read-only n 0x0 0xFFFFFFFF DCOIR_CONSTK_RSEL5 DCOIR_CONSTK_RSEL5 DCO IR mode: DCO Constant (K) for DCORSEL 5 0x68 32 read-only n 0x0 0xFFFFFFFF DCOIR_FCAL_RSEL04 DCOIR_FCAL_RSEL04 DCO IR mode: Frequency calibration for DCORSEL 0 to 4 0x4C 32 read-only n 0x0 0xFFFFFFFF DCOIR_FCAL_RSEL5 DCOIR_FCAL_RSEL5 DCO IR mode: Frequency calibration for DCORSEL 5 0x50 32 read-only n 0x0 0xFFFFFFFF DEVICE_ID DEVICE_ID Device ID 0xC 32 read-only n 0x0 0xFFFFFFFF DEVICE_INFO_LEN DEVICE_INFO_LEN Device Info Length 0x8 32 read-only n 0x0 0xFFFFFFFF DEVICE_INFO_TAG DEVICE_INFO_TAG Device Info Tag 0x4 32 read-only n 0xB 0xFFFFFFFF DIE_REC_LEN DIE_REC_LEN Die Record Length 0x20 32 read-only n 0x0 0xFFFFFFFF DIE_REC_TAG DIE_REC_TAG Die Record Tag 0x1C 32 read-only n 0xC 0xFFFFFFFF DIE_XPOS DIE_XPOS Die X-Position 0x24 32 read-only n 0x0 0xFFFFFFFF DIE_YPOS DIE_YPOS Die Y-Position 0x28 32 read-only n 0x0 0xFFFFFFFF END TLV_END TLV End Word 0x148 32 read-only n 0xBD0E11D 0xFFFFFFFF FLASH_INFO_LEN FLASH_INFO_LEN Flash Info Length 0x10C 32 read-only n 0x0 0xFFFFFFFF FLASH_INFO_TAG FLASH_INFO_TAG Flash Info Tag 0x108 32 read-only n 0x4 0xFFFFFFFF FLASH_MAX_ERASE_PULSES FLASH_MAX_ERASE_PULSES Flash Maximum Erase Pulses 0x114 32 read-only n 0x0 0xFFFFFFFF FLASH_MAX_PROG_PULSES FLASH_MAX_PROG_PULSES Flash Maximum Programming Pulses 0x110 32 read-only n 0x0 0xFFFFFFFF HWREV HWREV HW Revision 0x10 32 read-only n 0x0 0xFFFFFFFF LOT_ID LOT_ID Lot ID 0x30 32 read-only n 0x0 0xFFFFFFFF RANDOM_NUM_1 RANDOM_NUM_1 32-bit Random Number 1 0x120 32 read-only n 0x0 0xFFFFFFFF RANDOM_NUM_2 RANDOM_NUM_2 32-bit Random Number 2 0x124 32 read-only n 0x0 0xFFFFFFFF RANDOM_NUM_3 RANDOM_NUM_3 32-bit Random Number 3 0x128 32 read-only n 0x0 0xFFFFFFFF RANDOM_NUM_4 RANDOM_NUM_4 32-bit Random Number 4 0x12C 32 read-only n 0x0 0xFFFFFFFF RANDOM_NUM_LEN RANDOM_NUM_LEN 128-bit Random Number Length 0x11C 32 read-only n 0x0 0xFFFFFFFF RANDOM_NUM_TAG RANDOM_NUM_TAG 128-bit Random Number Tag 0x118 32 read-only n 0xD 0xFFFFFFFF REF_1P2V REF_1P2V REF 1.2V Reference 0xFC 32 read-only n 0x0 0xFFFFFFFF REF_1P45V REF_1P45V REF 1.45V Reference 0x100 32 read-only n 0x0 0xFFFFFFFF REF_2P5V REF_2P5V REF 2.5V Reference 0x104 32 read-only n 0x0 0xFFFFFFFF REF_CAL_LEN REF_CAL_LEN REF Calibration Length 0xF8 32 read-only n 0x0 0xFFFFFFFF REF_CAL_TAG REF_CAL_TAG REF Calibration Tag 0xF4 32 read-only n 0x8 0xFFFFFFFF RESERVED0 RESERVED0 Reserved 0x34 32 read-only n 0x0 0xFFFFFFFF RESERVED1 RESERVED1 Reserved 0x38 32 read-only n 0x0 0xFFFFFFFF RESERVED10 RESERVED10 Reserved 0x80 32 read-only n 0x0 0xFFFFFFFF RESERVED11 RESERVED11 Reserved 0x9C 32 read-only n 0x0 0xFFFFFFFF RESERVED12 RESERVED12 Reserved 0xA0 32 read-only n 0x0 0xFFFFFFFF RESERVED13 RESERVED13 Reserved 0xA4 32 read-only n 0x0 0xFFFFFFFF RESERVED14 RESERVED14 Reserved 0xA8 32 read-only n 0x0 0xFFFFFFFF RESERVED15 RESERVED15 Reserved 0xAC 32 read-only n 0x0 0xFFFFFFFF RESERVED16 RESERVED16 Reserved 0xB0 32 read-only n 0x0 0xFFFFFFFF RESERVED17 RESERVED17 Reserved 0xB4 32 read-only n 0x0 0xFFFFFFFF RESERVED18 RESERVED18 Reserved 0xB8 32 read-only n 0x0 0xFFFFFFFF RESERVED19 RESERVED19 Reserved 0xBC 32 read-only n 0x0 0xFFFFFFFF RESERVED2 RESERVED2 Reserved 0x3C 32 read-only n 0x0 0xFFFFFFFF RESERVED20 RESERVED20 Reserved 0xC0 32 read-only n 0x0 0xFFFFFFFF RESERVED21 RESERVED21 Reserved 0xC4 32 read-only n 0x0 0xFFFFFFFF RESERVED22 RESERVED22 Reserved 0xC8 32 read-only n 0x0 0xFFFFFFFF RESERVED23 RESERVED23 Reserved 0xCC 32 read-only n 0x0 0xFFFFFFFF RESERVED24 RESERVED24 Reserved 0xD0 32 read-only n 0x0 0xFFFFFFFF RESERVED25 RESERVED25 Reserved 0xD4 32 read-only n 0x0 0xFFFFFFFF RESERVED26 RESERVED26 Reserved 0xD8 32 read-only n 0x0 0xFFFFFFFF RESERVED3 RESERVED3 Reserved 0x54 32 read-only n 0x0 0xFFFFFFFF RESERVED4 RESERVED4 Reserved 0x58 32 read-only n 0x0 0xFFFFFFFF RESERVED5 RESERVED5 Reserved 0x5C 32 read-only n 0x0 0xFFFFFFFF RESERVED6 RESERVED6 Reserved 0x60 32 read-only n 0x0 0xFFFFFFFF RESERVED7 RESERVED7 Reserved 0x74 32 read-only n 0x0 0xFFFFFFFF RESERVED8 RESERVED8 Reserved 0x78 32 read-only n 0x0 0xFFFFFFFF RESERVED9 RESERVED9 Reserved 0x7C 32 read-only n 0x0 0xFFFFFFFF ROM_DRVLIB_REV ROM_DRVLIB_REV ROM Driver Library Revision 0x18 32 read-only n 0x0 0xFFFFFFFF TEST_RESULTS TEST_RESULTS Test Results 0x40 32 read-only n 0x0 0xFFFFFFFF WAFER_ID WAFER_ID Wafer ID 0x2C 32 read-only n 0x0 0xFFFFFFFF WDT_A WDT_A WDT_A 0x40004800 0x0 0xE registers n WDT_A_IRQ WDT_A Interrupt 3 WDTCTL CTL Watchdog Timer Control Register 0xC 16 read-write n 0x6904 0xFFFF WDTCNTCL Watchdog timer counter clear 3 1 write-only WDTCNTCL_enum_write write WDTCNTCL_0 No action 0 WDTCNTCL_1 WDTCNT = 0000h 1 WDTHOLD Watchdog timer hold 7 1 read-write WDTHOLD_0 Watchdog timer is not stopped 0 WDTHOLD_1 Watchdog timer is stopped 1 WDTIS Watchdog timer interval select 0 3 read-write WDTIS_0 Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) 0 WDTIS_1 Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) 1 WDTIS_2 Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) 2 WDTIS_3 Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) 3 WDTIS_4 Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) 4 WDTIS_5 Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) 5 WDTIS_6 Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) 6 WDTIS_7 Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) 7 WDTPW Watchdog timer password 8 8 read-write WDTSSEL Watchdog timer clock source select 5 2 read-write WDTSSEL_0 SMCLK 0 WDTSSEL_1 ACLK 1 WDTSSEL_2 VLOCLK 2 WDTSSEL_3 BCLK 3 WDTTMSEL Watchdog timer mode select 4 1 read-write WDTTMSEL_0 Watchdog mode 0 WDTTMSEL_1 Interval timer mode 1